
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATMTraffic Management Device
Released
Datasheet
80
Figure 53 shows the receive DRAM external memory 100 MHz write timing.
Twesu
Tweh
Trds
Write enable setup time
Write enable hold time
Required setup time (read data)
/RX_DRAM_WE
/RX_DRAM_WE
RX_DRAM_DATA(31:0)
2.8
1.5
0
ns
ns
ns
Figure 53. Receive DRAM External Memory 100 MHz Write Timing
Symbol
Parameter
Signals
Min
Max
Unit
Tcyc
Tch
Tcl
Taddrsu
Taddrh
Tbasu
Tbah
Tckh
Tcksu
Trassu
Trash
Tcassu
Tcash
Tcssu
Tcsh
Clock period
Clock high period
Clock low period
Address setup time
Address hold time
Bank address setup time
Bank address hold time
Clock enable hold time *
Clock enable setup time *
RAS setup time
RAS hold time
CAS setup time
CAS hold time
Chip select setup time
Chip select hold time
RX_DRAM_CLK
RX_DRAM_CLK
RX_DRAM_CLK
RX_DRAM_ADD(8:0)
RX_DRAM_ADD(8:0)
RX_DRAM_BA
RX_DRAM_BA
DRAM_CKE
DRAM_CKE
/RX_DRAM_RAS
/RX_DRAM_RAS
/RX_DRAM_CAS
/RX_DRAM_CAS
/RX_DRAM_CS(1:0)
/RX_DRAM_CS(1:0)
10
3
3
2.7
1.3
2.9
1.5
*
*
3.1
1.5
3.2
1.5
2.4
2.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
Signals
Min
Max
Unit
1
2
3
4
5
6
7
8
Tcyc
Tch
Tcl
Tcksu
Tckh
Tcssu
Tcsh
Trassu
Trash
Tcassu
Tcash
Taddrsu
Taddrh
Twesu
Tweh
Tdsu
VALID DATA
Tdh
Tbasu
Tbah
ROW
COLUMN
VALID DATA
VALID DATA
RX_DRAM_CLK
DRAM_CKE
/RX_DRAM_CS(1:0)
/RX_DRAM_RAS
/RX_DRAM_CAS
RX_DRAM_ADD(8:0)
/RX_DRAM_WE
RX_DRAM_DATA(31:0)
RX_DRAM_BA