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参数资料
| 型号： | PowerNP NPe405H |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式处理器) |
| 中文描述： | 32位嵌入式处理器（32位嵌入式处理器） |
| 文件页数： | 12/64页 |
| 文件大小： | 1050K |
| 代理商： | POWERNP NPE405H |
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Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
12
Supports HDLC protocol as well as a Transparent mode
One channel per port, autonomous management of the I-Frame and S-Frame of the Normal Response
mode (NRM) protocol
Software emulation of NRM mode
HDLCMP Interface
HDLC controller core providing eight full-duplex serial ports
Up to 2Mbps data rate
Supports HDLC protocol as well as a Transparent mode
Software emulation of NRM mode
General Purpose IO (GPIO) Controller
Two GPIO functions
- System GPIO (SGPIO)
- Communications GPIO (CGPIO)
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses
Most GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose. Both GPIO functions have 32 I/Os.
Each GPIO output is separately programmable to emulate an open-drain driver (drives to zero, three-
stated if output bit is 1)
Universal Interrupt Controller (UIC)
Two cascaded Universal Interrupt Controllers (UICs) provides the control, status, and communications
necessary between the various sources of interrupts and the local PowerPC processor.
Features include:
Supports 7 external and 49 internal interrupts
Edge triggered or level-sensitive
Positive or negative active
Non-critical or critical interrupt to PPC405 processor core
Programmable critical interrupt priority ordering
Programmable critical interrupt vector for faster vector processing
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