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参数资料
| 型号： | PowerPC 405GP |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC结构嵌入式控制器） |
| 文件页数： | 12/58页 |
| 文件大小： | 878K |
| 代理商： | POWERPC 405GP |
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PowerPC 405GP Embedded Processor Data Sheet
12
General Purpose IO (GPIO) Controller
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses
All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose. Twenty-three GPIOs are multiplexed with:
- 7 of 8 chip selects
- All seven external interrupts
- All nine instruction trace pins
Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three-
stated if output bit is 1)
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between
the various sources of interrupts and the local PowerPC processor.
Features include:
Supports 7 external and 19 internal interrupts
Edge triggered or level-sensitive
Positive or negative active
Non-critical or critical interrupt to PPC405 processor core
Programmable critical interrupt priority ordering
Programmable critical interrupt vector for faster vector processing
10/100 Mbps Ethernet MAC
Capable of handling full/half duplex 100Mbps and 10Mbps operation
Uses the Medium Independent Interface (MII) to the physical layer (PHY not included on chip)
JTAG
IEEE 1149.1 Test Access Port
IBM RISCWatch Debugger support
JTAG Boundary Scan Description Language (BSDL)
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