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参数资料
| 型号： | PowerPC 405GP |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC结构嵌入式控制器） |
| 文件页数： | 32/58页 |
| 文件大小： | 878K |
| 代理商： | POWERPC 405GP |
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PowerPC 405GP Embedded Processor Data Sheet
32
Signal List
The table following table provides a summary of the number of package pins associated with each functional
interface group.
In the table “Signal Functional Description” on page 33, each external signal is listed along with a short
description of the signal function. Some signals are multiplexed on the same package pin (ball) so that the pin
can be used for different functions. Multiplexed signals are shown as a default signal followed by a secondary
signal in square brackets (for example, C0:3[BE0:3]) The two signals are described consecutively within each
functional description. Active-low signals such as BE0:3 are marked with an overline.
It is expected that in any single application a particular pin will always be programmed to serve the same
function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller
address pins are used as outputs by the PPC405GP to broadcast an address to external slave devices when
the PPC405GP has control of the external bus. When, during the course of normal chip operation, an external
master gains ownership of the external bus, these same pins are used as inputs which are driven by the
external master and received by the EBC in the PPC405GP. In this example, the pins are also bidirectional,
serving as both inputs and outputs.
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs
only during reset and are used for other functions during normal operation (see “Strapping” on page 56). Note
that these are
not multiplexed
pins since the function of the pins is not programmable.
The following table lists all of the I/O signals provided by the PPC405GP. Please refer to “Signals Listed
Alphabetically” on page 16 for the pin number to which each signal is assigned.
Pin Summary
Group
No. of Pins
413-Ball package
456-Ball Package
35 mm
27mm
PCI
60
60
60
Ethernet
18
18
18
SDRAM
71
71
71
External peripheral
96
96
96
External master
9
9
9
Internal peripheral
15
15
15
Interrupts
7
7
7
JTAG
5
5
5
System
19
19
19
Total Signal Pins
300
300
300
OV
DD
V
DD
Gnd
38
32
24
22
24
24
26
60
56
Thermal (and Gnd)
15
36
36
Reserved
12
4
16
Total Pins
413
456
456
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