参数资料
型号: PowerPC 405GP
厂商: IBM Microeletronics
英文描述: 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器)
中文描述: 32位RISC嵌入式控制器(32位的RISC结构嵌入式控制器)
文件页数: 39/58页
文件大小: 878K
代理商: POWERPC 405GP
PowerPC 405GP Embedded Processor Data Sheet
39
PerAddr0
PerAddr1
PerAddr2
PerAddr3
PerAddr4
PerAddr5
PerAddr6
PerAddr7
PerAddr8
PerAddr9
PerAddr10
PerAddr11
PerAddr12
PerAddr13
PerAddr14
PerAddr15
PerAddr16
PerAddr17
PerAddr18
PerAddr19
PerAddr20
PerAddr21
PerAddr22
PerAddr23
PerAddr24
PerAddr25
PerAddr26
PerAddr27
PerAddr28
PerAddr29
PerAddr30
PerAddr31
Peripheral address bus used by PPC405GP when not in external
master mode, otherwise used by external master.
Note:
PerAddr0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerPar0
PerPar1
PerPar2
PerPar3
Peripheral byte parity signals
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0
PerWBE1
PerWBE2
PerWBE3
As outputs, these pins can act as byte-enables which are valid for
an entire cycle or as write-byte-enables which are valid for each
byte on each data transfer, allowing partial word transactions. As
outputs, pins are used by either peripheral controller or DMA
controller depending upon the type of transfer involved. Used as
inputs when external bus master owns the external interface
I/O
5V tolerant
3.3V LVTTL
1, 2
PerCS0
Peripheral chip select bank 0
O
5V tolerant
3.3V LVTTL
2
PerCS1[GPIO10]
PerCS2[GPIO11]
PerCS3[GPIO12]
PerCS4[GPIO13]
PerCS5[GPIO14]
PerCS6[GPIO15]
PerCS7[GPIO16]
Seven additional peripheral chip selects
or
General Purpose I/O - To access this function, software must
toggle a DCR register bit.
O[I/O]
5V tolerant
3.3V LVTTL
[mux’d]
1,2
Signal Functional Description
(Part 7 of 12)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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