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参数资料
| 型号： | PowerPC 405GP |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC结构嵌入式控制器） |
| 文件页数： | 43/58页 |
| 文件大小： | 878K |
| 代理商： | POWERPC 405GP |
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PowerPC 405GP Embedded Processor Data Sheet
43
System Interface
SysClk
Main system clock input
I
5V tolerant
3.3V LVTTL
Rcvr
SysReset
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. The
PPC405GP then holds the output low for 8192 cycles to reset all
internal and external logic connected to SysReset. A system reset
can also be initiated by software. Implemented as open-drain l
(two output states; 0 or open circuit).
I/O
5V tolerant
3.3V LVTTL
Rcvr
1, 2
AV
DD
Clean voltage input for the PLL
I
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
GPIO1[TS1E]
GPIO2[TS2E]
General Purpose I/O
or
Even Trace execution status.To access this function, software
must toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO3[TS1O]
GPIO4[TS2O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software
must toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1 (A22, AF18),
6 (AF18 only)
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
General Purpose I/O
Trace status. To access this function, software must toggle a
DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 4
GPIO9[TrcClk]
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the
CPU core frequency. To access this function, software must
toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 4
TestEn
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
I
5V tolerant
Rcvr w/ PD
3
RcvrInh
Receiver Inhibit. Used only for manufacturing tests. Pull up for
normal operation.
I
5V tolerant
Rcvr
2
DrvrInh1
DrvrInh2
Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up
for normal operation.
I
5V tolerant
Rcvr
2
TmrClk
This input must toggle at a rate of less than one half the CPU core
frequency (less than 100MHz in most cases). In most cases this
input toggles much slower (in the 1MHz to 10MHz range).
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
Signal Functional Description
(Part 11 of 12)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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