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参数资料
| 型号： | PowerPC 405GP |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC结构嵌入式控制器） |
| 文件页数： | 9/58页 |
| 文件大小： | 878K |
| 代理商： | POWERPC 405GP |
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PowerPC 405GP Embedded Processor Data Sheet
9
Supports processor access to all PCI address spaces:
- Single-byte PCI I/O reads and writes
- PCI memory single-beat and prefetch-burst reads and single-beat writes
- Single-byte PCI configuration reads and writes (type 0 and type 1)
- PCI interrupt acknowledge
- PCI special cycle
Supports PCI target access to all PLB address spaces
Supports PowerPC processor boot from PCI memory
SDRAM Memory Controller
The PPC405GP Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to four logical banks. Up to
256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
Memory bus operates at same frequency as PLB
32-bit memory interface support
Programmable address compare for each bank of memory
- 4GB of address space
Industry standard 168-pin DIMMS are supported (some configurations)
Up to 133MHz Memory, includes PC133 support
4MB to 256MB per bank
Programmable address mapping and timing
Auto refresh
Page Mode Accesses with up to 4 open pages
Sync DRAM configuration via mode set command
Power Management (self-refresh)
Error Checking and Correction (ECC) support
- Standard SEC/DED coverage
- Aligned nibble error detect
- Address error logging
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