R01UH0197EJ0120 Rev.1.20
Jul 21, 2011
M16C/6B Group
11. DMAC
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0 to 3), as well as by an interrupt
request which is generated by any function specified by bits DMS and DSEL4 to DSEL0 in the DMiSL register.
However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control
register, so that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are
always accepted. Furthermore, because the DMAC does not affect interrupts, the IR bit in the interrupt control register
does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register = 1
(DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the
number of transfer requests generated and the number of times data is transferred may not match. Refer to 11.4 “DMA i = 0 to 3
NOTES:
1.
DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the interrupt
control register.
2.
The selectable factors of DMA requests differ with each channel.
3.
Make sure that no DMAC-related registers (addresses 0180h to 01BFh) are accessed by the DMAC.
Table 11.1
Item
Specification
No. of channels
4 (cycle steal method)
Transfer memory space
From given address in the 1-Mbyte space to a fixed address
From a fixed address to given address in the 1-Mbyte space
From a fixed address to a fixed address
Maximum No. of bytes
transferred
128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
Falling edge of INT0 to INT1
Both edges of INT0 to INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to 2 transmission interrupt requests
UART0 to 2 reception/ACK interrupt requests
A/D conversion interrupt requests (64-pin version only)
Software triggers
Channel priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 takes precedence)
Transfer unit
8 bits or 16 bits
Transfer address direction
Forward or fixed (The source and destination addresses cannot both be in the
forward direction.)
Transfer mode Single transfer
Transfer is completed when the DMAi transfer counter underflows.
Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value of the DMAi
transfer counter reload register and a DMA transfer is continued with it.
DMA interrupt request
generation timing
When the DMAi transfer counter underflowed
DMA transfer start
Data transfer is initiated each time a DMA request is generated when the DMAE bit
in the DMAiCON register = 1 (enabled).
DMA transfer
stop
Single transfer
When the DMAE bit is set to 0 (disabled)
After the DMAi transfer counter underflows
Repeat transfer When the DMAE bit is set to 0 (disabled)
Reload timing for forward
address pointer and DMAi
transfer counter
When a data transfer is started after setting the DMAE bit to 1 (enabled), the forward
address pointer is reloaded with the value of the SARi or DARi pointer whichever is
specified to be in the forward direction and the DMAi transfer counter is reloaded
with the value of the DMAi transfer counter reload register.
DMA transfer cycles
Minimum 3 cycles between SFR and internal RAM