R01UH0197EJ0120 Rev.1.20
Jul 21, 2011
M16C/6B Group
13. Serial Interface
13.1.2
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data
i = 0 to 2
NOTES:
1.
If an overrun error occurs, the receive data of the UiRB register will be indeterminate. The IR bit in the SiRIC
register does not change.
2.
Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register. U2IRS bit is in U2C1 register.
3.
The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
from the UARTi receive register to the UiRB register.
Table 13.5
UART Mode Specifications
Item
Specification
Transfer data format
Character bit (transfer data): selectable from 7, 8, or 9 bits
Start bit: 1 bit
Parity bit: selectable from odd, even, or none
Stop bit: selectable from 1 bit or 2 bits
Transfer clock
The CKDIR bit in the UiMR register = 0 (internal clock): fj / (16 (n + 1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: setting value of UiBRG register 00h to FFh
CKDIR bit = 1 (external clock): fEXT / (16 (n + 1))
fEXT: input from CLKi pin n: setting value of UiBRG register 00h to FFh
Transmission,
reception control
Selectable from CTS function, RTS function or CTS/RTS function disabled
Transmission start
condition
Before transmission starts, satisfy the following requirements
The TE bit in the UiC1 register = 1 (transmission enabled)
The TI bit in the UiC1 register = 0 (data present in the UiTB register)
If CTS function is selected, input on the CTSi pin = “L”
Reception start condition
Before reception starts, satisfy the following requirements
The RE bit in the UiC1 register = 1 (reception enabled)
Start bit detection
Interrupt request
generation timing
For transmission, one of the following conditions can be selected
The UiIRS bit
(2) = 0 (transmit buffer empty):
when transferring data from the UiTB register to the UARTi transmit register (at start of
transmission)
The UiIRS bit = 1 (transfer completed):
when the serial interface completes sending data from the UARTi transmit register
For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
This error occurs if the serial interface started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
This error occurs when the number of stop bits set is not detected
This error occurs when if parity is enabled, the number of 1 in parity and character bits
does not match the number of 1 set
Error sum flag
This flag is set to 1 when any of the overrun, framing, or parity errors occur
Select function
LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be
selected
Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits are
not reversed.
TXD, RXD I/O polarity switch
This function reverses the polarities of the TXD pin output and RXD pin input. The logic
levels of all I/O data are reversed.
Separate CTS/RTS pins (UART0)
CTS0 and RTS0 are input/output from separate pins.