R01UH0197EJ0120 Rev.1.20
Jul 21, 2011
M16C/6B Group
13. Serial Interface
i = 0 to 2
NOTES:
1.
If the source or factor of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be
set to 1 (interrupt requested). (Refer to 20.5 “Interrupt”.) If one of the bits shown below is changed, the interrupt source, the interrupt
timing, etc. change. Therefore, always be sure to clear the IR bit to 0 (interrupt not requested) after changing those bits.
Bits SMD2 to SMD0 in the UiMR register, the IICM bit in the UiSMR register, the IICM2 bit in the UiSMR register, and the CKPH bit in the
UiSMR3 register.
2.
Set the initial value of SDAi output while bits SMD2 to SMD0 in the UiMR register = 000b (serial interface disabled).
3.
Second data transfer to the UiRB register (rising edge of SCLi 9th bit).
4.
First data transfer to the UiRB register (falling edge of SCLi 9th bit).
5.
6.
7.
When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to 1 (factor of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR27 bit in the IFSR2A register to 1 (factor of interrupt: UART1 bus collision).
Table 13.13
I2C Mode Functions
Function
Clock Synchronous Serial
I/O Mode
(SMD2 to SMD0 = 001b,
IICM = 0)
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
Factor of interrupt number
–
Start condition detection or stop condition detection
Factor of interrupt number
UARTi transmission
Transmission started or
completed (selected by
UiIRS)
No acknowledgment detection (NACK)
Rising edge of SCLi 9th bit
UARTi transmission
Rising edge of SCLi
9th bit
UARTi transmission
Falling edge of SCLi
next to the 9th bit
Factor of interrupt number
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Acknowledgment detection (ACK)
Rising edge of SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Timing for transferring
data from the UART
reception shift register to
the UiRB register
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Rising edge of SCLi 9th bit
Falling edge of SCLi
9th bit
Falling and rising
edges of SCLi 9th
bit
UARTi transmission
output delay
Not delayed
Delayed
Functions of TXDi/SDAi
TXDi output
SDAi input/output
Functions of RXDi/SCLi
RXDi input
SCLi input/output
Functions of CLKi
CLKi input or output port
selected
– (Cannot be used in I2C mode)
Noise filter width
15 ns
200 ns
Read RXDi and SCLi pin
levels
Possible when the
corresponding port
direction bit = 0
Always possible no matter how the corresponding port direction bit is set
Initial value of TXDi and
SDAi outputs
CKPOL = 0 (“H”)
CKPOL = 1 (“L”)
The value set in the port register before setting I2C mode (2) Initial and end values of
SCLi
–
“H”
“L”
“H”
“L”
UARTi reception
Acknowledgment detection (ACK)
UARTi reception
Falling edge of SCLi 9th bit
Store received data
1st to 8th bits of the
received data are stored
into bits 0 to 7 in the
UiRB register
1st to 8th bits of the received data are
stored into bits 7 to 0 in the UiRB register
1st to 7th bits of the received data are
stored into bits 6 to 0 in the UiRB register.
8th bit is stored into bit 8 in the UiRB
register
1st to 8th bits are
stored into bits 7 to
0 in the UiRB
Read Received Data
The UiRB register status is read
Bits 6 to 0 in the
UiRB register are
read as bits 7 to 1.
Bit 8 in the UiRB
register is read as