R01UH0197EJ0120 Rev.1.20
Jul 21, 2011
M16C/6B Group
7. Clock Generation Circuit
Figure 7.4
CM2 Register
NOTES:
1.
Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
2.
When the CM20 bit is set to 1 (oscillation stop and re-oscillation detection function enabled), the CM27 bit is
set to 1 (oscillation stop and re-oscillation detection interrupt), and the CPU clock source is the main clock, the
CM21 bit is set to 1 (125 kHz on-chip oscillator clock) if the main clock stop is detected.
3.
If the CM20 bit is set to 1 and the CM23 bit is set to 1 (main clock stops), do not set the CM21 bit to 0.
4.
This bit is set to 1 when the main clock stop is detected and the main clock re-oscillation is detected. When
this flag changes state from 0 to 1, an oscillation stop or a re-oscillation detection interrupt is generated. Use
this bit in an interrupt routine to determine the factors of interrupts between the oscillation stop, re-oscillation
detection interrupt and the watchdog timer interrupt. This bit is set to 0 by writing 0 in a program.
(This bit remains unchanged even if a 1 is written. Nor is it set to 0 when an oscillation stop or a re-oscillation
detection interrupt request is acknowledged.) When the CM22 bit is set to 1 and an oscillation stop or a re-
oscillation is detected, an oscillation stop or a re-oscillation detection interrupt is not generated.
5.
Determine the main clock status by reading the CM23 bit several times in an oscillation stop or a re-oscillation
detection interrupt routine.
6.
This bit is valid when the CM07 bit in the CM0 register is set to 0.
7.
When the PM21 bit in the PM2 register is set to 1 (disable clock modification), this bit remains unchanged
even if writing to the CM20 bit.
8.
Set the CM20 bit to 0 (disabled) before entering stop mode. Exit stop mode before setting the CM20 bit back
to 1 (enabled).
9.
Set the CM20 bit in the CM2 register to 0 (disabled) before setting the CM05 bit in the CM0 register to 1 (main
clock stops).
10. Bits CM20, CM21, and CM27 remain unchanged at the oscillation stop detection reset.
11. When the CM21 bit is set to 0 (main clock) and the CM05 bit is set to 1 (main clock stops), the CM06 bit fixed
to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capacity high).
b7
0
b6 b5 b4
b1
b2
b3
Oscillation Stop Detection Register (1)
Symbol
CM2
Address
000Ch
Bit Symbol
Bit Name
RW
After Reset
0X000010b (10)
b0
Function
CM20
Oscillation stop and
re-oscillation detection enable
bit (7, 8, 9,10)
0: Oscillation stop and re-oscillation
detection function disabled
1: Oscillation stop and re-oscillation
detection function enabled
RW
CM21
System clock select
bit 2 (2, 3, 6, 10, 11)
RW
0: Main clock
1: 125 kHz on-chip oscillator clock
CM22
Oscillation stop and
re-oscillation detection
flag (4)
RW
0: Main clock stops and re-oscillation not
detected
1: Main clock stops and re-oscillation
detected
CM23
XIN monitor flag (5)
RO
0: Main clock oscillates
1: Main clock stops
—
(b5-b4)
Reserved bits
Set to 0
RW
—
(b6)
No register bit. If necessary, set to 0. Read as undefined value.
—
CM27
Operation select bit
(when an oscillation stops and
re-oscillation is detected) (10)
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation detection
interrupt
RW