28. Serial Communications Interface (SCIc, SCId)
28.7.1
Generation of Start, Restart, and Stop Conditions
Writing 1 to the IICSTAREQ bit in SIMR3 causes the generation of a start condition. The generation of a start condition
proceeds through the following operations.
The level on the SSDAn line falls (from the high level to the low level) and the SSCLn line is kept in the released
state.
The hold time for the start condition is secured as half of a bit period at the bit rate determined by the setting of the
BRR.
The level on the SSCLn line falls (from the high level to the low level), the IICSTAREQ bit in SIMR3 is cleared (to
0), and a start-condition generated interrupt is output.
Writing 1 to the IICRSTAREQ bit in SIMR3 causes the generation of a start condition. The generation of a start
condition proceeds through the following operations.
The SSDAn line is released and the SSCLn line is kept at the low level.
The period at low level for the SSCLn line is secured as half of a bit period at the bit rate determined by the setting
of the BRR.
The SSCLn line is released (transition from the low to the high level).
Once the high level on the SSCLn line is detected, the setup time for the restart condition is secured as half of a bit
period at the bit rate determined by the setting of the BRR.
The level on the SSDAn line falls (from the high level to the low level).
The hold time for the restart condition is secured as half of a bit period at the bit rate determined by the setting of the
BRR.
The level on the SSCLn line falls (from the high level to the low level), the IICRSTAREQ bit in SIMR3 is cleared
(to 0), and a restart-condition generated interrupt is output.
Writing 1 to the IICRSTPREQ bit in SIMR3 causes the generation of a stop condition. The generation of a stop condition
proceeds through the following operations.
The level on the SSDAn line falls (from the high level to the low level) and the SSCLn line is kept at the low level.
The period at low level for the SSCLn line is secured as half of a bit period at the bit rate determined by the setting
of the BRR.
The SSCLn line is released (transition from the low to the high level).
Once the high level on the SSCLn line is detected, the setup time for the stop condition is secured as half of a bit
period at the bit rate determined by the setting of the BRR.
The SSDAn is released (transition from the low to the high level), the IICSTPREQ bit in SIMR3 is cleared (to 0),
and a stop-condition generated interrupt is output.
S:
Indicates a start condition, i.e. the master device changing the level on the SSDAn line from the high to the low level
while the SSCLn line is at the high level.
SLA:
Indicates a slave address, by which the master device selects a slave device.
R/W#:
Indicates the direction of transfer (reception or transmission). The value 1 corresponds to transfer from the slave device
to the master device and 0 corresponds to transfer from the master device to the slave device.
A/A#:
Indicates an acknowledge bit. This is returned by the slave device for master transmission and by the master device for
master reception. Return of the low level indicates ACK and return of the high level indicates NACK.
Sr:
Indicates a restart condition, i.e. the master device changing the level on the SSDAn line from the high to the low level
while the SSCLn line is at the high level and after the setup time has elapsed.
DATA:
Indicates the data being received or transmitted.
P:
Indicates a stop condition, i.e. the master device changing the level on the SSDAn line from the low to the high level
while the SSCLn line is at the high level.