REVISION HISTORY
Under development Preliminary document
Specifications in this document are tentative and subject to change.
0.90
Aug. 09, 2011
456
Figure 17.13 Example of Operation when Transfer Information Skip is Executed, changed
458
Table 17.9 Execution Cycles of the DTC: Note 7. added
18. Event Link Controller (ELC)
478
Table 18.6 Operations of Modules when Event is Input, changed
483
18.3.6 Procedure for Linking Events: Description changed
484
18.4.1 Setting the ELSR18 and ELSR19 Registers: Description changed
484
18.4.2 Setting the Bit-Rotating Operation of the Output Port Groups: Description changed
19.I/O Ports
505
19.2.1 Port Direction Register (PDR): Description changed
506
19.2.2 Port Output Data Register (PODR): Description changed
508
19.2.4 Port mode register (PMR): Description changed
509
19.2.5 Open Drain Control Register 0 (ODR0): Description changed
510
19.2.6 Open Drain Control Register 1 (ODR1): Description changed
512
19.2.8 Drive Capacity Control Register (DSCR): Description changed
513
Table 19.6 Treatment of Unused Pins, changed
20. Multi-Function Pin Controller (MPC)
515
Table 20.1 Allocation of Pin Functions to Multiple Pins: NMI added
549, 550
Table 20.31 Setting up the External Bus Interface, changed
20.4 Notes on Register Setting, deleted
551, 552
20.4.2 Notes on MPC Register Setting: Description changed
21. Multi-Function Timer Pulse Unit 2 (MTU2)
All in this
section
Terms, changed: operate normally → normal mode
Term used for ELC, changed: Count clear operation → Count restart operation
555
Table 21.2 MTU2A Functions, changed
593
21.2.17 Timer Output Master Enable Registers (TOER): Description changed
714
21.6.25 Continuous Output of Compare-Match Pulse Interrupt Signal, added
22. Port Output Enable 2 (POE2)
753
22.2.7 Input Level Control/Status Register 3 (ICSR3): Description changed
754, 755
22.3 Operation: Description changed
759
22.5 Usage Notes: Description changed
23. 8-Bit Timer (TMR)
All in this
section
Terms, changed: Internal clock → Frequency dividing clock
Term used for ELC, changed: Count clear operation → Count restart operation
23.7 and 23.8, exchanged
761
Table 23.2 Pin Configuration of TMR, changed
762
Figure 23.1 Block Diagram of TMR (Unit 0), changed
763
Figure 23.2 Block Diagram of TMR (Unit 1), changed
771, 772
23.2.6 Timer Control/Status Register (TCSR): Note 1 changed
773
23.2.7 Time Count Start Register (TCSTR): Description changed
774
23.3.1 Pulse Output: Description changed
779
Figure 23.10 Timing of Clearance by External Reset (Rising Edge), changed
779
Figure 23.11 Timing of Clearance by External Reset (High Level), changed
783
23.7.1 Event Signal Output to ELC: Description changed
24. Compare Match Timer (CMT)
All in this
section
Terms, changed: Internal clock → Frequency dividing clock
Term used for ELC, changed: Count clear operation → Count restart operation
799
24.5.2 (2) Event Count: Description changed
24.6.4 Point for Caution When Changing the Value of CMCR, deleted
24.6.5 Point for Caution Regarding the Counter (CMCNT) and CMCOR, deleted
25. Realtime Clock (RTC)
All in this
section
Term used in RTC description, changed: software reset → RTC software reset
801
Table 25.1 Specifications of RTCA, changed
803
Table 25.3 Registers of RTCA: Value after reset changed (Register descriptions also changed),
Note 1 added
822
25.2.20 Time Error Adjustment Register (RADJ): Description changed
832
Figure 25.4 Setting the Time, changed
843
25.6.4 Transitions to Low Power Consumption Modes after Setting Registers: Description changed
843
25.6.5 Points for Caution When Writing to and Reading from Registers: Description changed
Rev.
Date
Description
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Summary