29. I2C Bus Interface (RIIC)
29.
I2C Bus Interface (RIIC)
The RX210 Group has one I2C bus interface (RIIC module). The RIIC module conforms with and provides a subset of the NXP I2C bus (Inter-IC-Bus) interface functions.
29.1
Overview
an example of I/O pin connections to external circuits (I2C bus configuration example). Table 29.2 lists the I/O pins of the RIIC.
Table 29.1
RIIC Specifications (1/2)
Item
Specifications
Communications format
I2C bus format or SMBus format
Master mode or slave mode selectable
Automatic securing of the various set-up times, hold times, and bus-free times for the transfer rate
Transfer rate
Up to 400 kbps
SCL clock
For master operation, the duty cycle of the SCL clock is selectable in the range from 4% to 96%.
Issuing and detecting
conditions
Start, restart, and stop conditions are automatically generated. Start conditions (including restart conditions)
and stop conditions are detectable.
Slave address
Up to three slave-address settings can be made.
Seven- and ten-bit address formats are supported (along with the use of both at once).
General call addresses, device ID addresses, and SMBus host addresses are detectable.
Acknowledgement
For transmission, the acknowledge bit is automatically loaded.
Transfer of the next data for transmission can be automatically suspended on detection of a not-
acknowledge bit.
For reception, the acknowledge bit is automatically transmitted.
If a wait between the eighth and ninth clock cycles has been selected, software control of the value in the
acknowledge field in response to the received value is possible.
Wait function
In reception, the following periods of waiting can be obtained by holding the clock signal (SCL) at the low
level:
Waiting between the eighth and ninth clock cycles
Waiting between the ninth clock cycle and the first clock cycle of the next transfer (WAIT function)
SDA output delay
function
Timing of the output of transmitted data, including the acknowledge bit, can be delayed.
Arbitration
For multi-master operation
Operation to synchronize the SCL (clock) signal in cases of conflict with the SCL signal from another
master is possible.
When issuing the start condition would create conflict on the bus, loss of arbitration is detected by testing
for non-matching between the internal signal for the SDA line and the level on the SDA line.
In master operation, loss of arbitration is detected by testing for non-matching between the signal on the
SDA line and the internal signal for the SDA line.
Loss of arbitration due to detection of the start condition while the bus is busy is detectable (to prevent the
issuing of double start conditions).
Loss of arbitration in transfer of a not-acknowledge bit due to the internal signal for the SDA line and the
level on the SDA line not matching is detectable.
Loss of arbitration due to non-matching of internal and line levels for data is detectable in slave
transmission.
Timeout function
The internal time-out function is capable of detecting long-interval stop of the SCL (clock signal).
Noise removal
The interface incorporates digital noise filters for both the SCL and SDA signals, and the width for noise
cancellation by the filters is adjustable by software.
Interrupt sources
Four sources:
Error in transfer or occurrence of events (detection of AL, NACK, time-out, a start condition including a
restart condition, or a stop condition)
Receive-data-full (including matching with a slave address)
Transmit-data-empty (including matching with a slave address)
Transmission complete
Low power consumption
function
Module stop state can be set.