15. Buses
15.5
Operation of CS Area Controller
15.5.1
Separate Bus
The various periods in the timing charts are described below.
The CS area controller (CSC) operates in synchronization with the external bus clock (BCLK). The operation cycles,
such as wait cycles specified with the CSC register, are counted on BCLK. In the following description, frequencies of
BCLK and BCLK pin output are the same, unless otherwise noted.
The external bus access is started at the rising edge of the BCLK pin output pulse. However, when the external bus clock
(BCLK) frequency and BCLK pin output frequency are different, if two or more rounds of external bus access are
generated in response to a single transfer request from the bus master, the second and subsequent rounds of the external
bus access may be started at the falling edge of the BCLK pin output pulse according to the wait settings (see
Figure(a) Tw1 to Twn (Clock Cycles of Waiting for a Normal Read Cycle or Normal Write Cycle)
The period Tw1 to Twn is made up of the number of clock cycles between the start of access via the external bus clock
and one cycle before the strobe signal is valid. The number of cycles is selectable within the range from zero to 31.
Within this period, the timing of CSn#, RD#, and WRn# assertion (placing the signals at the low level) is determined by
the respective wait settings. Specifically, the periods of waiting are controlled by the CS assert wait select bits (CSON),
the RD assert wait select bits (RDON), the WR assert wait select bits (WRON), and the write data output wait select bits
(WDON) of CSn wait control register 2 (CSnWCR2). The number of clock cycles for each of these periods of waiting is
selectable as a value from zero to seven counted from the start of external bus access. Selectable numbers of cycles are
also within the overall number of clock cycles of waiting for reading or writing.
(b) Tend (Clock Cycle where the Strobe Signal is Valid)
Tend is the next clock cycle after completion of the period of waiting for a normal cycle of reading or writing or for a
cycle of page reading or page writing. If each wait select bit for a normal cycle of reading or writing or for a cycle of
page reading or page writing is zero, the clock cycle where bus access starts is the clock cycle where the strobe signal is
valid. The RD# and WRn# signals are negated in the next clock cycle after the cycle where the strobe signal is valid. In
the case of read access, the clock cycle where the strobe signal is valid becomes the clock cycle where the data to be read
are sampled.
If an external wait is enabled, the wait signal is sampled at the time of the cycle where the strobe signal is valid. The bus
cycle is extended if the wait signal is at the low level. The bus cycle is completed in the next clock cycle if the wait signal
is at the high level. Tend indicates the cycle where sampling of the wait signal starts.
After the first cycle where the strobe signal is valid during page access, second and subsequent page access operations
(point 5. below) start in the next cycle except in cases of write access where a setting (other than zero) for write-data
output extension clock cycles (point 4. below) has been made. If the setting for the RD or WR assertion wait is a value
other than zero, the RD# and WRn# signals are negated in the next clock cycle. If the setting is zero, assertion continues.
Furthermore, the CSn# signal continues to be asserted rather than being negated.
(c) Tn1 to Tnm (Clock Cycles of CS Extension)
In the case of normal access, Tn1 to Tnm represent the clock cycles of the period following the cycle where the strobe
signal is valid (Tend) up to negation of the CSn# signal. For read or write access, the timing of negation can be controlled
by the read-access CS extension cycle select bits (CSROFF) and the write-access CS extension cycle select bits
(CSWOFF) in the CSn wait control register 2 (CSnWCR2), respectively.
The number of cycles is counted from the cycle following the cycle where the strobe signal is valid.
In the case of page access, Tn1 to Tnm represent the clock cycles of the period for the cycle following the last cycle
where the strobe signal is valid up to negation of the CSn# signal.
For write access, setting the write data output extension cycle select bits (WDOFF) controls extension of the period
where the address and output data are valid.