30. Serial Peripheral Interface (RSPI)
30.3.11
Clock Synchronous Operation
Setting the SPMS bit in the RSPI control register (SPCR) to 1 selects clock synchronous operation of the RSPI. In clock
synchronous operation, the SSLAi pin is not used, and the three pins of RSPCKA, MOSIA, and MISOA handle
communications. The SSLAi pin is available as I/O port pins.
Although clock synchronous operation does not require use of the SSLAi pin, operation of the module is the same as in
SPI operation. That is, in both master and slave operations, communications can be performed with the same flow as in
SPI operation. However, mode fault errors are not detected because the SSLAi pin is not used.
Furthermore, operation is not guaranteed if clock synchronous operation proceeds when the SPCMDm.CPHA bit is set to
0 in slave mode (SPCR.MSTR = 0).
30.3.12
Master Mode Operation
(1) Starting a Serial Transfer
The RSPI updates the data in the transmit buffer (SPTX) of SPDR when data is written to the RSPI data register (SPDR)
with the transmit buffer being empty (data for the next transfer is not set). When the shift register is empty after the
number of frames set in the SPDCR.SPFC[1:0] bits are written to the SPDR, the RSPI copies data from the transmission
buffer to the shift register and starts serial transmission. Upon copying transmit data to the shift register, the RSPI
changes the status of the shift register to “full”, and upon termination of serial transfer, it changes the status of the shift
register to “empty”. The status of the shift register cannot be referenced.
(2) Terminating a Serial Transfer
The RSPI terminates the serial transfer after transmitting an RSPCKA edge corresponding to the sampling timing. If free
space is available in the receive buffer, upon termination of serial transfer, the RSPI copies data from the shift register to
the receive buffer of the RSPI data register (SPDR).
It should be noted that the final sampling timing varies depending on the bit length of transfer data. In master mode, the
RSPI data length depends on the SPCMDm.SPB[3:0] bit setting.
However, transfer in clock-synchronous operation is conducted without the SSLA0 output signal.
(3) Sequence Control
The transfer format employed in master mode is determined by SPSCR, SPCMDm, SPBR, SPCKD, SSLND, and SPND
registers. Although the SSLAi signals are not output in clock synchronous operation, these settings are valid.
SPSCR is a register used to determine the sequence configuration for serial transfers that are executed by the RSPI in
master mode. The following items are set in SPCMDm register: SSLAi output signal value, MSB/LSB first, data length,
some of the bit rate settings, RSPCKA polarity/phase, whether SPCKD is to be referenced, whether SSLND is to be
referenced, and whether SPND is to be referenced. SPBR holds some of the bit rate settings; SPCKD, an RSPI clock
delay value; SSLND, an SSL negation delay; and SPND, a next-access delay value.
According to the sequence length that is assigned to SPSCR, the RSPI makes up a sequence comprised of a part or all of
SPCMDm register. The RSPI contains a pointer to the SPCMDm register that makes up the sequence. The value of this
pointer can be checked by reading the SPSSR.SPCP[2:0] bits. When the SPE bit in the RSPI control register (SPCR) is
set to 1 and the RSPI function is enabled, the RSPI loads the pointer to the commands in SPCMD0 register, and
incorporates the SPCMD0 register setting into the transfer format at the beginning of serial transfer. The RSPI
increments the pointer each time the next-access delay period for a data transfer ends. Upon completion of the serial
transfer that corresponds to the final command comprising the sequence, the RSPI sets the pointer in SPCMD0 register,
and in this manner the sequence is executed repeatedly.