R01UH0040EJ0100 Rev.1.00
Page 205 of 1657
Sep 8, 2011
RX630 Group
7. Option-Setting Memory
7.2
Register Descriptions
7.2.1
Option Function Select Register 0 (OFS0)
Address(es): FFFF FF8Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
———
WDTRS
TIRQS
WDTRPSS[1:0] WDTRPES[1:0]
WDTCKS[3:0]
WDTTOPS[1:0] WDTST
RT
—
Value after reset:
The value set by the user*1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
IWDTS
LCSTP
—
IWDTR
STIRQS
IWDTRPSS[1:0] IWDTRPES[1:0]
IWDTCKS[3:0]
IWDTTOPS[1:0] IWDTS
TRT
—
Value after reset:
The value set by the user*1
Note 1. The value of the blank product is FFFF FFFFh. It is set to the written value after written by the user.
Bit
Symbol
Bit Name
Description
R/W
b0
—
Reserved
When reading, this bit returns to the value written by the
user. The write value should be 1.
R
b1
IWDT Start Mode Select
0: IWDT is automatically activated in auto-start mode after a
reset
1: IWDT is halted after a reset
R
b3, b2
IWDT Timeout Period Select
b3 b2
0 0: 1024 cycles (03FFh)
0 1: 4096 cycles (0FFFh)
1 0: 8192 cycles (1FFFh)
1 1: 16384 cycles (3FFFh)
R
b7 to b4
IWDT Clock Frequency
Division Ratio Select
b7
b4
0 0 0 0: LOCO (Cycle period: 131 ms)
0 0 1 0: LOCO/16 (Cycle period: 2.10 s)
0 0 1 1: LOCO/32 (Cycle period: 4.19 s)
0 1 0 0: LOCO/64 (Cycle period: 8.39 s)
1 1 1 1: LOCO/128 (Cycle period: 16.8 s)
0 1 0 1: LOCO/256 (Cycle period: 33.6 s)
Settings other than above are prohibited.
R
b9, b8
IWDT Window End Position
Select
b9 b8
0 0: 75%
0 1: 50%
1 0: 25%
1 1: 0% (No window end position setting)
R
b11, b10
IWDT Window Start Position
Select
b11 b10
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100% (No window start position setting)
R
b12
IWDT Reset Interrupt
Request Select
0: Non-maskable interrupt request is enabled
1: Reset is enabled
R
b13
—
Reserved
When reading, this bit returns to the value written by the
user. The write value should be 1.
R
b14
IWDT Sleep Mode Count
Stop Control
0: Counting stop is disabled
1: Counting stop is enabled when entering sleep, software
standby, deep software standby, or all-module clock stop
mode
R
b16, b15
—
Reserved
When reading, this bit returns to the value written by the
user. The write value should be 1.
R
b17
WDT Start Mode Select
0: WDT is automatically activated in auto-start mode after a
reset
1: WDT is stopped after a reset
R