R01UH0040EJ0100 Rev.1.00
Page 112 of 1657
Sep 8, 2011
RX630 Group
2. CPU
2.
CPU
The RX630 Group is an MCU with the high-speed, high-performance RX CPU as its core.
A variable-length instruction format has been adopted for the RX CPU. Allocating the more frequently used instructions
to the shorter instruction lengths facilitates the development of efficient programs that take up less memory.
The CPU has 73 basic instructions and 8 floating-point operation instructions, and nine DSP instructions, for a total of 90
instructions. It has 10 addressing modes and caters to register–register operations, register–memory operations,
immediate–register operations, immediate–memory operations, memory–memory transfer, and bitwise operations. High-
speed operation was realized by achieving execution in a single cycle not only for register–register operations, but also
for other types of multiple instructions. The CPU includes an internal multiplier and an internal divider for high-speed
multiplication and division.
The RX CPU has a five-stage pipeline for processing instructions. The stages are instruction fetching, instruction
decoding, execution, memory access, and write-back. In cases where pipeline processing is drawn-out by memory
access, subsequent operations may in fact be executed earlier. By adopting “out-of-order completion” of this kind, the
execution of instructions is controlled to optimize numbers of clock cycles.
2.1
Features
High instruction execution rate: One instruction in one clock cycle
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73 (arithmetic/logic instructions, data-transfer instructions, branch instructions, bit-manipulation
instructions, string-manipulation instructions, and system-manipulation instructions)
Relative branch instructions to suit branch distances
Variable-length instruction format (lengths from one to eight bytes)
Short formats for frequently used instructions
Floating-point operation instructions: 8
DSP instructions: 9
Supports 16-bit
16-bit multiplication and multiply-and-accumulate operations.
Rounds the data in the accumulator.
Addressing modes: 10
Five-stage pipeline
Adoption of out-of-order completion
Processor modes
A supervisor mode and a user mode are supported.
Floating-point operation unit
Supports single-precision (32-bit) floating point
Supports data types and exceptions in conformance with the IEEE754 standard
Data arrangement
Selectable as little endian or big endian