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R01UH0040EJ0100 Rev.1.00
Page 132 of 1657
Sep 8, 2011
RX630 Group
2. CPU
2.8.2
Instructions and Pipeline Processing
The operands in the table below indicate the following meaning.
#IMM: Immediate
flag: bit, flag
Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register
CR: Control register
dsp: displacement
pcdsp: displacement
2.8.2.1
Instructions Converted into Single Micro-Operation and Pipeline Processing
The table below lists the instructions that are converted into a single micro-operation. The number of cycles in the table
indicates the number of cycles during no-wait memory access.
Note 1. The number of cycles for the dividing instruction varies according to the divisor and dividend.
Table 2.13
Instructions that are Converted into a Single Micro-Operation
Instruction
Mnemonic (indicates the common operation when
the size is omitted)
Reference
Figure
Number of
Cycles
Arithmetic/logic instructions
(register-register, immediate-register)
Except EMUL, EMULU, RMPA, DIV,
DIVU and SATR
{ABS, NEG, NOT} “Rd”/“Rs, Rd”
{ADC, MAX, MIN, ROTL, ROTR, XOR} “#IMM, Rd”/“Rs,
Rd”
ADD “#IMM, Rd”/“Rs, Rd”/“#IMM, Rs, Rd”/“Rs, Rs2, Rd”
{AND, MUL, OR, SUB} “#IMM, Rd”/“Rs, Rd”/“Rs, Rs2, Rd”
{CMP, TST} “#IMM, Rs”/“Rs, Rs2”
NOP
{ROLC, RORC, SAT} “Rd”
SBB “Rs, Rd”
{SHAR, SHLL, SHLR} “#IMM, Rd”/“Rs, Rd”/“#IMM, Rs,
Rd”
1
Arithmetic/logic instructions (division)
DIV “#IMM, Rd”/“Rs, Rd”
DIVU “#IMM, Rd”/“Rs, Rd”
Data transfer instructions
(register-register, immediate-register)
MOV “#IMM, Rd”/“Rs, Rd”
{MOVU, REVL, REVW} “Rs, Rd”
SCCnd “Rd”
{STNZ, STZ} “#IMM, Rd”
1
Transfer instructions (load operation)
{MOV, MOVU} “[Rs], Rd”/“dsp[Rs], Rd”/“[Rs+], Rd”/“[-Rs],
Rd”/“[Ri, Rb], Rd”
POP “Rd”
Throughput: 1
Transfer instructions (store operation)
MOV “Rs, [Rd]”/“Rs, dsp[Rd]”/“Rs, [Rd+]”/“Rs, [-Rd]”/“Rs,
[Ri, Rb]”/“#IMM, dsp[Rd]”/“#IMM, [Rd]”
PUSH “Rs”
PUSHC “CR”
SCCnd “[Rd]”/“dsp[Rd]”
1
Bit manipulation instructions (register)
{BCLR, BNOT, BSET} “#IMM, Rd”/“Rs, Rd”
BMCnd “#IMM, Rd”
BTST “#IMM, Rs”/“Rs, Rs2”
1
Branch instructions
BCnd “pcdsp”
{BRA, BSR} “pcdsp”/“Rs”
{JMP, JSR} “Rs”
Branch taken: 3
Branch not
taken: 1
Floating-point operation instructions
(register-register, immediate-register)
FCMP “#IMM, Rd”/“Rs, Rs2”
1
System manipulation instructions
{CLRPSW, SETPSW} “flag”
MVTC “#IMM, CR”/“Rs, CR”
MVFC “CR, Rd”
MVTIPL“#IMM”
—1
DSP instructions
{MACHI, MACLO, MULHI, MULLO} “Rs, Rs2”
{MVFACHI, MVFACMI} “Rd”
{MVTACHI, MVTACLO} “Rs”
RACW“#IMM”
1