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R01UH0040EJ0100 Rev.1.00
Page 139 of 1657
Sep 8, 2011
RX630 Group
2. CPU
(d)
When the load data is not used by the subsequent instruction
When the load data is not used by the subsequent instruction, the subsequent operations are in fact executed earlier and
the operation processing ends (out-of-order completion).
Figure 2.27
When Load Data is not Used by the Subsequent Instruction
2.8.3
Calculation of the Instruction Processing Time
Though the instruction processing time of the CPU varies according to the pipeline processing, the approximate time can
be calculated in the following methods.
When the load data is used by the subsequent instruction, the number of cycles described as “latency” is counted as
the number of cycles for the memory load instruction. For the cycles other than the memory load instruction, the
number of cycles described as “throughput” is counted.
If the instruction fetch stall is generated, the number of cycles increments.
Depending on the system configuration, multiple cycles are required for the memory access.
2.8.4
Numbers of Cycles for Response to Interrupts
Table 2.15 lists numbers of cycles taken by processing for response to interrupts.
Times calculated from the values in
Table 2.15 will be applicable when access to memory from the CPU is processed
with no waiting. The on-chip RAM and ROM in products of the RX630 Groups allow such access. Numbers of cycles
for response to interrupts can be minimized by placing program code (and vectors) in on-chip ROM and the stack in on-
chip RAM. Furthermore, place the addresses where the exception handling routine start on eight-byte boundaries.
For information on the number of cycles from notification to acceptance of the interrupt request, indicated by N in the
The timing of interrupt acceptance depends on the state of the pipelines. For more information on this, see
sectionTable 2.15
Numbers of Cycles for Response to Interrupts
Type of Interrupt Request/Details of Processing
Fast Interrupt
Other Interrupts
ICU
Judgment of priority order
2 cycles
CPU
Number of cycles from notification to acceptance of
the interrupt request
N cycles
(varies with the instruction being executed at the time the interrupt was
received)
CPU Pre-processing by hardware
Saving the current PC and PSW values in RAM
(or in control registers in the case of the fast interrupt)
Reading of the vector
Branching to the start of the exception handling
routine
4 cycles
6 cycles
IF
D
E
MOV [R1], R2
IF
D
E
M
WB
IF
D
E
WB
ADD R4, R5
SUB R6, R7
(mop) load
(mop) add
(mop) sub