- 您现在的位置：买卖IC网 > PDF目录192277 > S-812C52AY-Z-G 5.2 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PBCY3 PDF资料下载
参数资料
| 型号： | S-812C52AY-Z-G |
| 元件分类： | 固定正电压单路输出LDO稳压器 |
| 英文描述： | 5.2 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PBCY3 |
| 封装： | LEAD FREE, TO-92, 3 PIN |
| 文件页数： | 16/39页 |
| 文件大小： | 690K |
| 代理商： | S-812C52AY-Z-G |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页
W946432AD
23
WRITEs
The starting column and bank addresses are provided with the WRITE command, and AUTO PRECHARGE
is either enabled or disabled for that access. If AUTO PRECHARGE is enabled (A8=HIGH), the row being
accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is disabled (A8=LOW),
the row will remain open for subsequent accesses.
During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS
following the write command, and subsequent data elements will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command and the first rising edge is known as the write
preamble; the LOW state on DQS following the last data-in element is known as the write post amble. The
time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with
a relatively wide range (from 75% to 125% of 1 clock cycle), Figure12: show the two extremes of tDQSS for a
burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQS will
remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In
either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on
any positive edge of clock following the previous WRITE command. The first data element from the new
burst is applied after either the last element of a completed burst or the last desired data element of a longer
burst, which is being truncated. The new WRITE command should be issued
x cycles after the first WRITE
command, where
x equals the number of desired data element pairs Figure13: show concatenated bursts of
4. An example of non-consecutive WRITEs is shown in. 0 Full-speed random write accesses within a page or
pages can be performed as shown in. Figure15: Data for any WRITE burst may be followed by a subsequent
READ command. To follow a WRITE without truncating the write burst, tWTR should be met as shown in
Figure16:.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE
without truncating the write burst, tWR should be met as shown in 0.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in
Figure18:
Error! Reference source not found.. Note that only the data-in pairs that are registered prior to
the tWR period are written to the internal array, and any subsequent data-in should be masked with DM, as
shown in Figure18:
Error! Reference source not found.. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until t RP is met.
POWER-DOWN
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down
occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CK, CK and CKE. For maximum power savings, the user
has the option of disabling the DLL prior to entering power-down. In that case, the DLL must be enabled after
exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However,
power-down duration is limited by the refresh requirements of the device, so in most applications, the self-
refresh mode is preferred over the DLL-disabled power-down mode.
In power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM,
and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is
registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied
one clock cycle later.
相关PDF资料 |
PDF描述 |
|---|---|
| S-812C52BMC-C5GT2G | 5.2 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PDSO5 |
| S-81332HG-KC-S | 3.2 V FIXED POSITIVE REGULATOR, PSSO3 |
| S-81332HG-KC-T1 | 3.2 V FIXED POSITIVE REGULATOR, PSSO3 |
| S-81332HG-KC-T2 | 3.2 V FIXED POSITIVE REGULATOR, PSSO3 |
| S-814A33AUC-BCXT2G | 3.3 V FIXED POSITIVE LDO REGULATOR, 0.44 V DROPOUT, PDSO5 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S-812C52BMC-C5GT2G | 功能描述:低压差稳压器 - LDO Linear LDO Reg 1.0uA Iq 75mA Iout ON/OFF RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| S-812C52BMC-C5GT2U | 功能描述:IC REG LINEAR 75MA SOT23-5 制造商:ablic u.s.a. inc. 系列:* 包装:剪切带（CT） 零件状态:在售 稳压器数:1 电流 - 输出:75mA 工作温度:-40°C ~ 85°C（TA） 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商器件封装:SOT-23-5 标准包装:1 |
| S-812C52BPI-C5GTFG | 功能描述:低压差稳压器 - LDO Linear LDO Reg 1.0uA Iq 75mA Iout ON/OFF RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| S-812C52BPI-C5GTFU | 功能描述:IC REG LINEAR 75MA SNT6A 制造商:ablic u.s.a. inc. 系列:- 包装:剪切带（CT） 零件状态:在售 输出配置:正 输出类型:固定 稳压器数:1 电压 - 输入（最大值）:16V 电压 - 输出（最小值/固定）:5.2V 电压 - 输出（最大值）:- 压降（最大值）:0.25V @ 10mA 电流 - 输出:75mA 电流 - 静态（Iq):2.5μA PSRR:- 控制特性:使能 保护功能:短路 工作温度:-40°C ~ 85°C（TA） 安装类型:表面贴装 封装/外壳:6-SMD，扁平引线 供应商器件封装:SNT-6A（H） 标准包装:1 |
| S-812C53AMC-C3H-T2 | 功能描述:低压差稳压器 - LDO 5.3V 1.0uA 2.0% RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
发布紧急采购，3分钟左右您将得到回复。