参数资料
型号: S-812C52AY-Z-G
元件分类: 固定正电压单路输出LDO稳压器
英文描述: 5.2 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PBCY3
封装: LEAD FREE, TO-92, 3 PIN
文件页数: 8/39页
文件大小: 690K
代理商: S-812C52AY-Z-G
W946432AD
16
DESELECT
The Device Deselect command disables the command decoder so that the RAS CAS WE and Address
inputs are ignored. This command is similar to the No-Operation command.
NO OPERATION (NOP)
The No Operation Command should be used in cases when the DDR SDRAM is in an idle or a wait state to
prevent the DDR SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of the clock.
A No Operation Command will not terminate a previous operation that is still executing, such as a burst read
or write cycle.
MODE REGISTER SET
Command is registered when CS , RAS , CAS , and WE is at the rising edge of the clock. The mode
registers are loaded by inputs A0-A10. See mode register descriptions in the Register Definition section. The
MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress,
and a subsequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is registered when CS , RAS is low with CAS , and WE held high at the rising edge
of the clock, used to open a row in a particular bank for a subsequent access.
READ
The READ command is registered when CS , CAS is low with RAS , and WE held high at the rising edge of
the clock, used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-A7 selects the starting column location.
WRITE
The WRITE command is registered when CS , CAS , WE is low with RAS , held high at the rising edge of
the clock, used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-A7 selects the starting column location
PRECHARGE
The PRECHARGE command is registered when CS , RAS , WE is low with CAS held high at the rising
edge of the clock, used to deactivate the open row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a specified time ( tRP) after the PRECHARGE
command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any READ or WRITE commands being issued to that bank. A
PRECHARGE command will be treated as a NOP if there is no open row in that bank.
BURST READ STOP
The BURST READ STOP command register when CS WE is low with RAS CAS held high is used to
truncate read bursts (with autoprecharge disabled).
AUTO REFRESH
The Auto Refresh command is register when CS RAS CAS low with WE high.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t
Care” during an AUTO REFRESH command. The W946432AD requires AUTO REFRESH cycles at an
average periodic interval of 15.6s (maximum).
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