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| 型号： | S29CL032J0JFAM020 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件页数： | 71/79页 |
| 文件大小： | 2994K |
| 代理商： | S29CL032J0JFAM020 |
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March 30, 2009 S29CD-J_CL-J_00_B3
S29CD-J & S29CL-J Flash Family
73
Data
She e t
20. Appendix 2
20.1
Command Definitions
Legend
Notes
Table 20.1 Memory Array Command Definitions (x32 Mode)
Command (Notes)
Cy
c
le
s
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (5)1
RA
RD
Reset (6)1
XXX
F0
Autoselect
(7)
Manufacturer ID
4
555
AA
2AA
55
555
90
BA+X00
01
Device ID (8)
6
555
AA
2AA
55
555
90
BA+X01
7E
BA+X0E
09
BA+X0F
00/01
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (9)1
BA
B0
Program/Erase Resume (10)1
BA
30
55
98
Accelerated Program (13)
2
XX
A0
PA
PD
Configuration Register Verify (12)
3
555
AA
2AA
55
BA+555
C6
BA+XX
RD
Configuration Register Write (14)
4
555
AA
2AA
55
555
D0
XX
WD
Unlock Bypass Entry (15)
3
555
AA
2AA
55
555
20
Unlock Bypass Program (15)
2
XX
A0
PA
PD
Unlock Bypass Erase (15)
2
XX
80
XX
10
XX
98
Unlock Bypass Reset (15)
2
XX
90
XX
00
BA = Bank Address. The set of addresses that comprise a bank. The system may
write any address within a bank to identify that bank for a command.
PA = Program Address (Amax–A0). Addresses latch on the falling edge of the
WE# or CE# pulse, whichever happens later.
PD = Program Data (DQmax–DQ0) written to location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Read Address (Amax–A0).
RD = Read Data. Data DQmax–DQ0 at address location RA.
SA = Sector Address. The set of addresses that comprise a sector. The system
may write any address within a sector to identify that sector for a command.
WD = Write Data. See “Configuration Register” definition for specific write data.
Data latched on rising edge of WE#.
X = Don’t care
1. See Table 8.1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write
operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table)
address bits higher than A11 (except where BA is required) and data bits
higher than DQ7 are don’t cares.
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to the read mode (or to the erase-
suspend-read mode if previously in Erase Suspend) when a bank is in the
autoselect mode, or if DQ5 goes high (while the bank is providing status
information).
7. The fourth cycle of the autoselect command sequence is a read cycle. The
system must provide the bank address to obtain the manufacturer ID or
device ID information. See “Autoselect” for more information.
8. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in
the sixth cycle indicates ordering option 00, 01h indicates ordering option 01.
9. The system may read and program in non-erasing sectors when in the
Program/Erase Suspend mode. The Program/Erase Suspend command is
valid only during a sector erase operation, and requires the bank address.
10. The Program/Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
11. Command is valid when device is ready to read array data.
12. Asynchronous read operations.
13. ACC must be at VID during the entire operation of this command.
14. Command is ignored during any Embedded Program, Embedded Erase, or
Suspend operation.
15. The Unlock Bypass Entry command is required prior to any Unlock Bypass
operation. The Unlock Bypass Reset command is required to return to the
read mode.
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