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| 型号： | S29GL032M10TAIR52 |
| 厂商： | Spansion Inc. |
| 英文描述： | CAP TANT 220UF 2.5V 20% POLY SMD |
| 中文描述： | MirrorBit闪存系列 |
| 文件页数： | 18/159页 |
| 文件大小： | 5216K |
| 代理商： | S29GL032M10TAIR52 |
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114
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
Data s he et
Table 36. Command Definitions (x8 Mode, BYTE# = VIL)
Command
Sequence
(Note 1)
Cyc
le
s
Bus Cycles (Notes 2–5)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data Addr Data
Read (Note 6)
1
RA
RD
Reset (Note 7)
1
XXX
F0
Au
to
se
le
ct
(
N
ot
e
8
)
Manufacturer ID
4
AAA
AA
555
55
AAA
90
X00
01
Device ID (Note 9)
4
AAA
AA
555
55
AAA
90
X02
7E
X1C
X1E
SecSi‰ Sector Factory Protect
4
AAA
AA
555
55
AAA
90
X06
(Note 10)
Sector Group Protect Verify (Note
4
AAA
AA
555
55
AAA
90
(SA)X04
00/01
Enter SecSi Sector Region
3
AAA
AA
555
55
AAA
88
Exit SecSi Sector Region
4
AAA
AA
555
55
AAA
90
XXX
00
Write to Buffer (Note 11)
3
AAA
AA
555
55
SA
25
SA
BC
PA
PD
WBL
PD
Program Buffer to Flash
1
SA
29
Write to Buffer Abort Reset (Note 13)
3
AAA
AA
555
55
AAA
F0
Chip Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
AAA
10
Sector Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
SA
30
Program/Erase Suspend (Note 14)
1
XXX
B0
Program/Erase Resume (Note 15)
1
XXX
30
CFI Query (Note 16)
1
AA
98
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
BC = Byte Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 on page 22 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or AAA as shown in table, address bits above A11 are don’t
care.
5. Unless otherwise noted, address bits A21–A11 are don’t cares.
6. No unlock or command cycles required when device is in read
mode.
7. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
8. Fourth cycle of autoselect command sequence is a read cycle.
Data bits DQ15–DQ8 are don’t care. See Autoselect Command
Sequence section or more information.
9. Device ID must be read in three cycles.
10. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
11. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
12. Total number of cycles in command sequence is determined by
number of bytes written to write buffer. Maximum number of
cycles in command sequence is 37, including “Program Buffer to
Flash” command.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
14. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
15. Erase Resume command is valid only during Erase Suspend
mode.
16. Command is valid when device is ready to read array data or
when device is in autoselect mode.
17. Refer to Table 18 on page 80, AutoSelect Codes for individual
Device IDs per device density and model number.
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