- 您现在的位置：买卖IC网 > PDF目录192299 > S29GL032M10TAIR52 (Spansion Inc.) CAP TANT 220UF 2.5V 20% POLY SMD PDF资料下载
参数资料
| 型号： | S29GL032M10TAIR52 |
| 厂商： | Spansion Inc. |
| 英文描述： | CAP TANT 220UF 2.5V 20% POLY SMD |
| 中文描述： | MirrorBit闪存系列 |
| 文件页数： | 23/159页 |
| 文件大小： | 5216K |
| 代理商： | S29GL032M10TAIR52 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
119
Da tash eet
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is,
the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that are selected for erasure. (The system
may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for
sector and mode information. Refer to Table 37 on page 120 to compare outputs for DQ2 and DQ6.
Figure 8, on page 118 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” ex-
plains the algorithm. See also the “RY/BY#: Ready/Busy#” on page 116 subsection. Figure 20, on page 134
shows the toggle bit timing diagram. Figure 21, on page 134 shows the differences between DQ2 and DQ6 in
graphical form.
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then de-
termine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went
high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation.
If it is still toggling, the device did not completed the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 did not go
high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining
the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the algorithm when it returns to determine the status of the
operation (top of Figure 6, on page 111).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device
halts the operation, and when the timing limit is exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset command to return the device to the reading the array (or to
erase-suspend-read if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure
started. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase command. When the time-out period
is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the
system can be assumed to be less than 50 s, the system need not monitor DQ3. See the “Sector Erase Command
Sequence” on page 110 section.
相关PDF资料 |
PDF描述 |
|---|---|
| S29GL032M10TAIR53 | CAP TANT 330UF 2.5V 20% POLY SMD |
| S29GL032M10TAIR60 | CAP TANT 470UF 4V 20% POLY SMD |
| S29GL032M10TAIR62 | CAP TANT 470UF 4V 20% POLY SMD |
| S29GL032M10TCCR22 | MirrorBit Flash Family |
| S29GL032M10TCCR23 | MirrorBit Flash Family |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S29GL032M10TAIR53 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10TAIR60 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10TAIR62 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10TAIR63 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10TBCR00 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
发布紧急采购，3分钟左右您将得到回复。