参数资料
型号: S29GL256N80FAI010
厂商: SPANSION LLC
元件分类: PROM
英文描述: MirrorBit Flash Family
中文描述: 16M X 16 FLASH 3V PROM, 80 ns, PBGA64
封装: 13 X 11 MM, 1MM PITCH, FBGA-64
文件页数: 88/110页
文件大小: 2624K
代理商: S29GL256N80FAI010
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
79
Ad va nc e
Inform ati o n
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 s, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must
provide an address within any of the sectors selected for erasure to read valid
status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 s, then the
device returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-
serted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may
be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
Table 14 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data#
Polling algorithm. Figure 17 in the AC Characteristics section shows the Data#
Polling timing diagram.
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