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参数资料
| 型号： | S3P9664-SM |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24 |
| 封装： | 0.300 INCH, SOP-24 |
| 文件页数： | 15/148页 |
| 文件大小： | 784K |
| 代理商： | S3P9664-SM |
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UNIVERSAL SERIAL BUS
S3C9664/P9664 (Preliminary Spec)
13-6
CONTROL ENDPOINT STATUS REGISTER (EP0CSR)
EP0CSR register controls Endpoint 0 (Control Endpoint), and also holds status bits for Endpoint 0. EP0CSR is
located at F1H and is read/write addressable.
Bit7
CLEAR_SETUP_END : MCU writes “1” to this bit to clear SETUP_END bit (bit4). This bit is
automatically cleared after clearing SETUP_END bit by SIE. So read value will be always “0”.
Bit6
CLEAR_OUT_PKT_RDY: MCU writes “1” to this bit to clear OUT_PKT_RDY bit (bit0). This bit is
automatically cleared after clearing OUT_PKT_RDY bit by USB block. So read value will be always “0”.
Bit5
SEND_STALL: MCU writes “1” to this bit to send STALL packet to Host, it must clear OUT_PKT_RDY
(bit 0) at the same time. If MCU receive invalid command then should write #60h to this register. The SIE
issues a STALL handshake to the current control transfer(Means next transaction). This bit will be
cleared after sending STALL handshake.
Bit4
SETUP_END : SIE sets this bit, when a control transfer ends without setting DATA_END bit (bit3). MCU
clears this bit, by writing a “1” to CLEAR_SETUP_END bit (bit7). When SIE sets this bit, an interrupt is
generated to MCU. When such condition occurs, SIE flushes the FIFO. MCU can not access to FIFO
until this bit cleared. This flag is a read only bit so MCU can not write to this bit directly.
Bit3
DATA_END: MCU sets this bit:
— After loading the last packet of data into the FIFO, and at the same time IN_PKT_RDY bit should be
set.
— While it clears OUT_PKT_RDY bit after unloading the last packet of data.
— For a zero length data phase, this bit should be set when it clears OUT_PKT_RDY bit.
Bit2
SENT_STALL: SIE sets this bit after send stall handshake to host. There are two cases which issue stall
packet to host. If MCU set SEND_STALL bit, then SIE will send stall to the next transaction and set this
bit. The other case is send stall by SIE automatically since protocol violation. An interrupt is generated
when this bit gets set. This bit is a read/write bit so MCU should clears this bit to end the STALL
condition.
Bit1
IN_PKT_RDY: MCU sets this bit, after loading data into Endpoint 0 FIFO. SIE clears this bit, once the
packet has been successfully sent to the host. An interrupt is generated when SIE clears this bit so that
MCU can load the next packet. For a zero length data phase, MCU sets IN_PKT_RDY bit without load
data to FIFO.
Bit0
OUT_PKT_RDY: SIE sets this bit, if the device receive valid data from host. An interrupt is generated,
when SIE sets this bit. MCU should download data and clears this bit by writing "1” to
CLEAR_OUT_PKT_RDY bit at the end of execution.
NOTES:
1.
When SETUP_END bit is set, OUT_PKT_RDY bit may also be set. This happens when the current transfer has
terminated by new setup transaction. In such case, MCU should first clear SETUP_END bit, and then start servicing the new
control transfer.
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S3P9688 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:8-bit single-chip CMOS microcontrollers |
| S3PDB100 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:Three Phase Rectifier Modules |
| S3PDB100N08 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:Three Phase Rectifier Modules |
| S3PDB100N12 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:Three Phase Rectifier Modules |
| S3PDB100N14 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:Three Phase Rectifier Modules |
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