参数资料
型号: SAB-C515-LM
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 16 MHz, MICROCONTROLLER, PQFP80
封装: PLASTIC, MQFP-80
文件页数: 36/162页
文件大小: 771K
代理商: SAB-C515-LM
Semiconductor Group
8-2
Fail Safe Mechanisms
C515
8.1.3 Refreshing the Watchdog Timer
Once started, the watchdog timer can only be cleared to 0000H by first setting bit WDT and with the
next instruction setting bit SWDT. Bit WDT will automatically be cleared during the second machine
cycle after having been set. For this reason, setting SWDT bit has to be a one cycle instruction (e.g.
SETB SWDT). This double instruction clearing of the watchdog timer was implemented to minimize
the chance of unintentionally clearing the watchdog. To prevent the watchdog from overflowing, it
must be cleared periodically.
Setting only bit SWDT does not reload the watchdog timer automatically to 0000H. A watchdog
timer reset operation occurs only by using the double instruction refresh sequence SETB WDT /
SETB SWDT.
8.1.4 Watchdog Reset and Watchdog Status Flag
lf the software fails to clear the watchdog in time, an internally generated watchdog reset is entered
at the counter state FFFCH and lasts four instruction cycles. This internal reset differs from an
external reset only to the extent that the watchdog timer is not disabled. Bit WDTS allows the
software to examine from which source the reset was initiated. lf it is set, the reset was caused by
a watchdog timer overflow.
Figure 8-1 shows a block diagram of the watchdog timer.
Figure 8-1
Block Diagram of the Watchdog Timer
MCB03210
Control Logic
WDT Reset if WDT count is between
IEN1
IEN0
)
(B8 H
H
A8
()
16-Bit Watchdog Timer
IP0 ( A9 H)
WDT
SWDT
-
External HW Reset
--
-
WDTS
OSC
f
÷ 12
Reset
FFFC HH
FFFF
-
PE/SWD
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