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| 型号： | SAB-C515-LM |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | PLASTIC, MQFP-80 |
| 文件页数： | 43/162页 |
| 文件大小： | 771K |
| 代理商： | SAB-C515-LM |
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Semiconductor Group
9-6
Power Saving Modes
C515
9.5
Power Down Mode
In the power down mode, the RC osciillator and the on-chip oscillator which operates with the XTAL
pins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents of
the on-chip RAM and the SFR's are maintained. The port pins, which are controlled by their port
latches, output the values that are held by their SFR's. The port pins which serve the alternate
output functions show the values they had at the end of the last cycle of the instruction which
initiated the power down mode. ALE and PSEN held at logic low level (see table 9-1).
In the power down mode of operation,
V
CC can be reduced to minimize power consumption. It must
be ensured, however, that is
V
CC not reduced before the power down mode is invoked, and that VCC
is restored to its normal operating level before the power down mode is terminated.
The power down mode can be left only by a hardware reset. Leaving the power down mode puts the
microcontroller with its SFRs into the reset state, and it should not be done before
V
CC is restored
to its nominal operating level.
9.5.1 Invoking Power Down Mode
The power down mode is entered by two consecutive instructions. The first instruction has to set the
flag bit PDE (PCON.1) and must not set bit PDS (PCON.6), the following instruction has to set the
start bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a
concurrent setting of both bits, PDE and PDS, does not initiate the power down mode. Bits PDE and
PDS will automatically be cleared after having been set and the value shown by reading one of
these bits is always 0. This double instruction is implemented to minimize the chance of
unintentionally entering the power down mode which could possibly ”freeze” the chip's activity in an
undesired status.
PCON is not a bit-addressable register, so the above mentioned sequence for entering the power
down mode is obtained by byte-handling instructions, as shown in the following example:
ORL
PCON,#00000010B
;set bit PDE, bit PDS must not be set
ORL
PCON,#01000000B
;set bit PDS, bit PDE must not be set, enter power down
The instruction that sets bit PDS is the last instruction executed before going into power down
mode. When the double instruction sequence shown above is used, the power down mode can only
be left by a reset operation.
Note : Before entering the power down mode, an A/D conversion in progress must be stopped.
9.5.2 Exit from Power Down Mode
If power down mode is exit via a hardware reset, the microcontroller with its SFRs is put into the
hardware reset state and the content of RAM is not changed. The reset signal that terminates the
power down mode also restarts the RC oscillator and the on-chip oscillatror. The reset operation
should not be activated before
V
CC is restored to its normal operating level and must be held active
long enough to allow the oscillator to restart and stabilize (similar to power-on reset).
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