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| 型号： | SC103335VR400B |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272 |
| 封装： | 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272 |
| 文件页数： | 4/72页 |
| 文件大小： | 978K |
| 代理商： | SC103335VR400B |
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MPC5200B Data Sheet, Rev. 4
12
Freescale Semiconductor
1.3
AC Electrical Characteristics
Hyperlinks to the indicated timing specification sections are provided below.
1.3.1
AC Test Timing Conditions:
Unless otherwise noted, all test conditions are as follows:
TA = –40 to 85 oC
Tj = –40 to 115 oC
VDD_CORE = 1.42 to 1.58 V
VDD_IO = 3.0 to 3.6 V
Table 11. e300 PLL Specifications
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
e300 frequency
fcore
(1)
1 The XLB_CLK frequency and e300 PLL Configuration bits must be chosen such that the resulting system
frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies in Table 12.
50
—
550
MHz
O4.1
e300 cycle time
tcore
2.85
—
40.0
ns
O4.2
e300 VCO frequency
fVCOcore
400
—
1200
MHz
O4.3
e300 input clock frequency
fXLB_CLK
—
25
—
367
MHz
O4.4
e300 input clock cycle time
tXLB_CLK
—
2.73
—
50.0
ns
O4.5
e300 input clock jitter
tjitter
(2)
2 This represents total input jitter—short term and long term combined—and is guaranteed by design. Two different
types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected.
Systemic jitter is passed into and through the PLL to the internal clock circuitry.
—
150
ps
O4.6
e300 PLL relock time
tlock
(3)
3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
—
100
μsO4.7
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