参数资料
| 型号： | SC16C852VIET,151 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 3/55页 |
| 文件大小： | 0K |
| 描述： | IC UART DUAL W/FIFO 36TFBGA |
| 标准包装： | 490 |
| 特点： | 可编程 |
| 通道数： | 2，DUART |
| FIFO's： | 128 字节 |
| 规程： | RS485 |
| 电源电压： | 2.5V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-TFBGA |
| 供应商设备封装： | 36-TFBGA（3.5x3.5） |
| 包装： | 托盘 |
| 其它名称： | 568-5662 935282518151 SC16C852VIET,151-ND SC16C852VIET-S SC16C852VIET-S-ND |
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SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
11 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[2]
These registers are accessible only when LCR[7] is a logic 1.
[3]
Second special registers are accessible only when EFCR[0] = 1.
[4]
Enhanced feature registers are only accessible when LCR = 0xBF.
[5]
First extra feature registers are only accessible when EFCR[2:1] = 01b.
[6]
Second extra feature registers are only accessible when EFCR[2:1] = 10b.
6.4 FIFO operation
6.4.1 32-byte FIFO mode
When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the
First Extra Register Set are empty (0x00) the transmit and receive trigger levels are set by
FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to
the SC16C652B (see Table 5), and the FIFO sizes are 32 entries. The transmit and
receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). It should be
noted that the user can set the transmit trigger levels by writing to the FCR, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a
time-out function to ensure data is delivered to the external CPU (see Section 6.8). Please
6.4.2 128-byte FIFO mode
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register
Set contains any value other than 0x00, the transmit and receive trigger levels are set by
TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the transmit
FIFO, and the transmit trigger levels can be set to any value between 1 and 128 with
granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive trigger
levels can be set to any value between 1 and 128 with granularity of 1.
When the effective FIFO size changes (that is, when FCR[0] toggles or when the
combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between
equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will
be lost).
6.5 Hardware flow control
When automatic hardware flow control is enabled, the SC16C852V monitors the CTSx pin
for a remote buffer overflow indication and controls the RTSx pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTSx transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C852V will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTSx input returns to a logic 0, indicating more data
may be sent.
Table 5.
Interrupt trigger level and flow control mechanism
(FCR[7:6, 5:4])
INTA/INTB pin activation
Negate RTSA/RTSB
or send Xoff
Assert RTSA/RTSB
or send Xon
RX
TX
[00, 00]
8
16
8
0
[01, 01]
16
8
16
7
[10, 10]
24
15
[11, 11]
28
30
28
23
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| SC16C852VIET-G | 功能描述:UART 接口集成电路 1.8V 2CH UART 128B FIFO 5MBPS RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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