参数资料
型号: SC16C852VIET,151
厂商: NXP Semiconductors
文件页数: 6/55页
文件大小: 0K
描述: IC UART DUAL W/FIFO 36TFBGA
标准包装: 490
特点: 可编程
通道数: 2,DUART
FIFO's: 128 字节
规程: RS485
电源电压: 2.5V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 36-TFBGA
供应商设备封装: 36-TFBGA(3.5x3.5)
包装: 托盘
其它名称: 568-5662
935282518151
SC16C852VIET,151-ND
SC16C852VIET-S
SC16C852VIET-S-ND
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
14 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.9 Programmable baud rate generator
The SC16C852V UART contains a programmable rational baud rate generator that takes
any clock input and divides it by a divisor in the range between 1 and (216
1). The
SC16C852V offers the capability of dividing the input frequency by rational divisor. The
fractional part of the divisor is controlled by the CLKPRES register in the First Extra
Register Set.
(1)
where:
N is the integer part of the divisor in DLL and DLM registers;
M is the fractional part of the divisor in CLKPRES register;
fXTAL1 is the clock frequency at XTAL1 pin.
Prescaler = 1 when MCR[7] is set to 0.
Prescaler = 4 when MCR[7] is set to 1.
A single baud rate generator is provided for the transmitter and receiver. The
programmable Baud Rate Generator (BRG) is capable of operating with a frequency of up
to 80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock
input. The SC16C852V can be configured for internal or external clock operation. For
internal clock operation, an industry standard crystal is connected externally between the
XTAL1 and XTAL2 pins (see Figure 7). Alternatively, an external clock can be connected
to the XTAL1 pin (see Figure 8) to clock the internal baud rate generator for standard or
custom rates (see Table 6).
The generator divides the input 16
× clock by any divisor from 1 to (216 1). The
SC16C852V divides the basic external clock by 16. The baud rate is configured via the
CLKPRES, DLL and DLM internal register functions. Customized baud rates can be
achieved by selecting the proper divisor values for the MSB and LSB sections of the baud
rate generator.
Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in Table 6
shows the selectable baud rate available when using a 1.8432 MHz external clock input
with MCR[7] is 0, and CLKPRES = 0x00.
Fig 6.
Prescalers and baud rate generator block diagram
baud rate
f
XTAL1
MCR 7
[]
16
N
M
16
------
+
×
-------------------------------------------------------------------
=
002aac645
OSCILLATOR
XTAL1
XTAL2
DIVIDE-BY-1
DIVIDE-BY-4
CLKPRES
[3:0]
BAUD RATE
GENERATOR
(DLL, DLM)
transmitter and
receiver clock
MCR[7] = 0
MCR[7] = 1
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