参数资料
型号: SC16C852VIET,151
厂商: NXP Semiconductors
文件页数: 54/55页
文件大小: 0K
描述: IC UART DUAL W/FIFO 36TFBGA
标准包装: 490
特点: 可编程
通道数: 2,DUART
FIFO's: 128 字节
规程: RS485
电源电压: 2.5V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 36-TFBGA
供应商设备封装: 36-TFBGA(3.5x3.5)
包装: 托盘
其它名称: 568-5662
935282518151
SC16C852VIET,151-ND
SC16C852VIET-S
SC16C852VIET-S-ND
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
8 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[1]
HVQFN48 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
RXA
D1
5
I
Receive data A, B. These inputs are associated with individual serial channel
data to the SC16C852V receive input circuits, A through B. The RX signal will
be a logic 1 during reset, idle (no data), or when not receiving data. During the
local Loopback mode, the RX input pin is disabled and TX data is connected to
the UART RX input, internally.
RXB
C2
4
I
RXRDYA
-31
O
Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR
status for individual receive channels (A to B). RXRDYn is primarily intended
for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0
indicates there is a receive data to read/upload, that is, receive ready status
with one or more RX characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed trigger level has not
been reached. This signal can also be used for single mode transfers (DMA
mode 0).
RXRDYB
-18
O
TXA
D2
7
O
Transmit data A, B. These outputs are associated with individual serial
transmit channel data from the SC16C852V. The TX signal will be a logic 1
during reset, idle (no data), or when the transmitter is disabled. During the local
Loopback mode, the TX output pin is disabled and TX data is internally
connected to the UART RX input.
TXB
E1
8
O
TXRDYA
-43
O
Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR
status for individual transmit channels (A to B). TXRDYn is primarily intended
for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual
channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is,
at lease one location is empty and available in the FIFO or THR. This pin goes
to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO
or THR. This signal can also be used for single mode transfers (DMA mode 0).
TXRDYB
-6
O
VDD
C4
42
I
Power supply input.
VSS
D4
I
Signal and power ground.
XTAL1
D3
13
I
Crystal or external clock input. Functions as a crystal input or as an external
clock input. A crystal can be connected between this pin and XTAL2 to form an
internal oscillator circuit. Alternatively, an external clock can be connected to
this pin to provide custom data rates (see Section 6.9 “Programmable baud
XTAL2
F2
14
O
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal
oscillator output or buffered clock output. Should be left open if an external
clock is connected to XTAL1.
Table 2.
Pin description …continued
Symbol
Pin
Type Description
TFBGA36
HVQFN48
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