参数资料
型号: SC2446ITETRT
厂商: Semtech
文件页数: 16/38页
文件大小: 0K
描述: IC SYNC STEP DOWN CTRLR 28-TSSOP
标准包装: 1
应用: 控制器,DDR
输入电压: 4.7 V ~ 16 V
输出数: 2
输出电压: 可调至 0.5V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 28-TSSOP 裸露焊盘
包装: 标准包装
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC2446ITEDKR
SC2446
POWER MANAGEMENT
Application Information (Cont.)
I Q 1 , rms = I o D ( 1 +
) .
current to reach its full-scale value I ds and
Q gd is the charge needed to charge gate-to-drain (Miller)
t r =
( Q gs 2 + Q gd ) R gt
t f =
( Q gs 2 + Q gd ) R gt
r
f
P tg =
MOSFET’s with low R ds(on) are used for the bottom switch.
MOSFET power dissipation consists of
a) conduction loss due to the channel resistance R ds(on) ,
b) switching loss due to the switch rise time t r and fall time
t f , and
c) the gate loss due to the gate resistance R G .
Top Switch:
The RMS value of the top switch current is calculated as
δ 2
12
The conduction losses are then
P tc = I Q1,rms2 R ds(on) .
R ds(on) varies with temperature and gate-source voltage.
Curves showing R ds(on) variations can be found in
manufacturers’ data sheet. From the Si4860 datasheet,
R ds(on) is less than 8m ? when V gs is greater than 10V.
However R ds(on) increases by 50% as the junction
temperature increases from 25 o C to 110 o C.
The switching losses can be estimated using the simple
formula
P ts = 21 ( t r + t f )( 1 + 2 δ ) I o V in f s .
where t r is the rise time and t f is the fall time of the switching
process. Different manufactures have different definitions
and test conditions for t and t . To clarify these, we sketch
the typical MOSFET switching characteristics under clamped
inductive mode in Figure 11.
Q gs2 is the additional gate charge required for the switch
.
capacitance when V ds is falling.
Switching losses occur during the time interval [ t 1 , t 3 ].
Defining t r = t 3 -t 1 and t r can be approximated as
.
V cc ? V gsp
where R gt is the total resistance from the driver supply rail
to the gate of the MOSFET. It includes the gate driver internal
impedance R gi , external resistance R ge and the gate
resistance R g within the MOSFET i.e.
R gt = R gi +R ge +R g .
V gsp is the Miller plateau voltage shown in Figure 11.
Similarly an approximate expression for t f is
.
V gsp
Only a portion of the total losses P g = Q g V cc f s is dissipated in
the MOSFET package. Here Q g is the total gate charge
specified in the datasheet. The power dissipated within
the MOSFET package is
R g
Q g V cc f s .
R gt
The total power loss of the top switch is then
P t = P tc +P ts +P tg .
If the input supply of the power converter varies over a
wide range, then it will be necessary to weigh the relative
importance of conduction and switching losses. This is
because conduction losses are inversely proportional
to the input voltage. Switching loss however increases
with the input voltage. The total power loss of MOSFET
should be calculated and compared for high-line and
low-line cases. The worst case is then used for thermal
design.
Gate charge
Figure 11. MOSFET switching characteristics
Bottom Switch:
The RMS current in bottom switch can be shown to be
In Figure 11,
Q gs1 is the gate charge needed to bring the gate-to-source
voltage V gs to the threshold voltage V gs_th ,
? 2004 Semtech Corp.
16
I Q 2 , rms = I o ( 1 ? D )( 1 +
δ 2
12
) .
www.semtech.com
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