参数资料
| 型号： | SC2544TSTRT |
| 厂商： | Semtech |
| 文件页数： | 12/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24TSSOP |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 300kHz |
| 占空比： | 90% |
| 电源电压： | 4.5 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC2544TSDKR |
SC2544
POWER MANAGEMENT
I Q 1 , rms = I o D ( 1 + 12 ) .
switch current to reach its full-scale value I ds , and Q gd
is the charge needed to charge gate-to-drain (Miller)
Applications Information (Cont.)
T op Switch
The RMS value of the top switch current is calculated
as
δ 2
The conduction losses are then
P tc = I Q1,rms 2 R ds(on) .
In Figure 9, Q gs1 is the gate charge needed to bring
the gate-to-source voltage V gs to the threshold voltage
V gs_th .
Q gs2 is the additional gate charge required for the
.
capacitance when V ds is falling.
Switching losses occur during the time interval [ t 1 ,
t 3 ]. Defining t r = t 3 -t 1 and t r can be approximated as
R ds(on) varies with temperature and gate-source
voltage. Curves showing R ds(on) variations can be found
in manufacturers ’ data sheet. From the Si4860
t r =
( Q gs 2 + Q gd ) R gt
V cc ? V gsp
.
datasheet, R ds(on) is less than 8m ? when V gs is greater
than 10V. However R ds(on) increases by 50% as the
junction temperature increases from 25 o C to 110 o C.
The switching losses can be estimated using the simple
where R gt is the total resistance from the driver supply
rail to the gate of the MOSFET. It includes the gate
driver internal impedance R gi , external resistance R ge
and the gate resistance R g within the MOSFET :
formula
P ts = 21 ( t r + t f )( 1 + 2 δ ) I o V in f s .
R gt = R gi +R ge +R g .
V gsp is the Miller plateau voltage shown in Figure 9.
Similarly an approximate expression for t f is
r
f
t f =
( Q gs 2 + Q gd ) R gt
where t r is the rise time and t f is the fall time of the
switching process. Different manufactures have
different definitions and test conditions for t and
t . To clarify these, we sketch the typical MOSFET
switching characteristics under clamped inductive
mode in Figure 9.
.
V gsp
Only a portion of the total losses P g = Q g V cc f s is
dissipated in the MOSFET package. Here Q g is the
total gate charge specified in the datasheet. The
V o lts
V ds
Ids
power dissipated within the MOSFET package is
M iller plateau
V gs
P tg =
R g
R gt
Q g V cc f s .
V gs th
Q gs1 Q gs2
Q gd
The total power loss of the top switch is then
P t = P tc +P ts +P tg .
t0
t1
t2
t3
G ate charge
If the input supply of the power converter varies
over a wide range, then it will be necessary to
Figure 9. MOSFET switching characteristics
weigh the relative importance of conduction and
switching losses. This is because conduction losses
are inversely proportional to the input voltage.
Switching loss however increases with the input
voltage. The total power loss of MOSFET should be
calculated and compared for high-line and low-line
cases. The worst case is then used for thermal
design.
? 2005 Semtech Corp.
14
www.semtech.com
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