参数资料
| 型号： | SC2544TSTRT |
| 厂商： | Semtech |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24TSSOP |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 300kHz |
| 占空比： | 90% |
| 电源电压： | 4.5 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC2544TSDKR |
SC2544
POWER MANAGEMENT
Applications Information (Cont.)
The compensator in Figure 10 includes an error am-
plifier and impedance networks Zf and Zs. It is imple-
mented by the circuit in Figure 12. The compensator
provides an integrator, double poles, and double ze-
ros. As shown in Figure 11, the integrator is used to
A resistive divider is used to program the output volt-
age. The top resistor R top of the divider in Fig. 12
can be chosen from 20k ? to 30k ? . Then the bot-
tom resistor R bot is found from:
boost the gain at low frequency. Two zeros are intro-
duced to compensate excessive phase lag at the
loop gain crossover due to the integrator (-90deg)
Rbot =
0 . 75 V
Vo ? 0 . 75 V
? Rtop
and the complex pole pair (-180deg). Two high fre-
quency poles are designed to compensate the ESR
zero and to attenuate high frequency noise.
where 0.75V is the internal reference voltage of the
SC2544.
The other components of the compensator can be
calculated using following design procedure:
(1). Plot the converter gain, including LC filter and
Fp1
C O M P E N S A T O R G A IN
Fp2
PWM modulator.
(2). Select the open loop crossover frequency Fc lo-
F z1
Fo
F z2
LO
OP
GA
IN
cated at 10% to 20% of the switching frequency. At
Fc, find the required DC gain.
Fz
CO
NV
ER
TE
R G
A IN
Fc
(3). Use the first compensator pole Fp1 to cancel the
ESR zero Fz.
(4). Have the second compensator pole Fp2 at half
the switching frequency to attenuate the switching
ripple and high frequency noise.
F R E Q U E N C Y (H z)
Fig. 11. Bode plots for control loop design.
C2
(5). Place the first compensator zero Fz1 at or below
50% of the power stage resonant frequency Fo.
(6). Place the second compensator zero Fz2 at or
below the power stage resonant frequency Fo.
A MathCAD program is available upon request for the
calculation of the compensation parameters.
Vc
C1
-
R2
C3
Rtop
R3
Vo
Out
E/A
+
Rbot
0.75V
Fig. 12. Compensation network.
? 2005 Semtech Corp.
16
www.semtech.com
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