参数资料
型号: SC2544TSTRT
厂商: Semtech
文件页数: 15/22页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24TSSOP
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 300kHz
占空比: 90%
电源电压: 4.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
包装: 标准包装
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC2544TSDKR
SC2544
POWER MANAGEMENT
Applications Information (Cont.)
PC Board Layout Issues
Circuit board layout is very important for the proper
operation of high frequency switching power con-
verters. A power ground plane is required to reduce
ground bounces. The followings are suggested for
proper layout.
P o w er Stage
1) Separate the power ground from the signal ground. In
SC2544 design, use an isolated local ground plane for
the controller and tie it to power grand.
2) Minimize the size of the high pulse current loop.
Keep the top MOSFET, the bottom MOSFET and the
input capacitors within a small area with short and
wide traces. In addition to the aluminum energy
storage capacitors, add multi-layer ceramic (MLC)
capacitors from the input to the power ground to
improve high frequency bypass.
3) Reduce high frequency voltage ringing. Widen and
shorten the drain and source traces of the MOSFETs
to reduce stray inductances. Add a small RC snubber
if necessary to reduce the high frequency ringing at
the phase node. Sometimes slowing down the gate
drive signal also helps in reducing the high frequency
ringing at the phase node if the EMI is a concern for
the system.
4) Shorten the gate drive trace. Integrity of the
gate drive (voltage level, leading and falling edges)
is important for circuit operation and efficiency. Short
and wide gate drive traces reduce trace inductances.
Bond wire inductance is about 2~3nH. If the length of
the PCB trace from the gate driver to the MOSFET
gate is 1 inch, the trace inductance will be about
25nH. If the gate drive current is 2A with 10ns rise
and falling times, the voltage drops across the bond
wire and the PCB trace will be 0.6V and 5V
respectively. This may slow down the switching
transient of the MOSFET ’s. These inductances may
also ring with the gate capacitance.
5) Put the decoupling capacitor for the gate drive power
supplies (BST and PVCC) close to the IC and power
ground.
Control Section
6) The frequency-setting resistor Rosc should be placed
close to Pin 23. Trace length from this resistor to the
analog ground should be minimized.
7) Place the bias decoupling capacitor right across
the VCC and analog ground AGND.
? 2005 Semtech Corp.
17
www.semtech.com
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