参数资料
| 型号： | SC2544TSTRT |
| 厂商： | Semtech |
| 文件页数： | 8/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24TSSOP |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 300kHz |
| 占空比： | 90% |
| 电源电压： | 4.5 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC2544TSDKR |
SC2544
POWER MANAGEMENT
Applications Information (Cont.)
Over Current Protection (OCP)
The inductor current is sensed by using the low side
MOSFET R ds(on) . After low side MOSFET is turned
on, the OCP comparator starts monitoring the
voltage drop across the MOSFET. The OCP trip
level is programmed by the resistor from the ILIM
pin to the phase node. There is an internal current
source that flows out of the ILIM pin which will
TG
I L
generate a voltage drop on the setting resistor.
When the sum of the setting resistor voltage and
100n S
B lan kin g
O C P A ctive
the MOSFET drain to source voltage is less then
zero, the OCP condition will be flagged. This
functionality is depicted in Figure 2.
The following formula is used to set the OCP level
10 μ A × R ILIM = I L _ PEAK × R DS ( ON )
When OCP is tripped, both high side and low side
MOSFETs will be turned off and this condition is
latched. At the same time, the soft start cap will
be discharged by the internal current source of
15uA. When the Vss drops bellow 0.65V, the DRVL
pin will go high again.
To avoid switching noise during the phase node
commutation, a 100nS blanking time is built in
after the low side MOSFET is turned on, as shown in
Fig. 3.
VCC
Figure 3. OCP comparator timing chart.
U nder Voltage Lock Out (UVLO)
The UVLO circuitry monitors Vcc and the soft start
begins once Vcc ramps up above 4.5V. There is a
built in 200mV hysteresis for the UVLO ramp down
threshold. The gate driver output will be in “tri-
state” (both high side and low side MOSFET off)
once Vcc ramps down bellow 4.2V (typical), and the
soft start cap will be discharged by internal 15uA
current sink.
Over Voltage Pro t ection (OVP)
The OVP circuitry monitors the feedback voltages,
If either feedback voltage exceeds 0.89V, the OVP
condition is registered. Under this condition, the
DRVH pins will be pulled low, and the DRVL pins will
be pulled high. This will create a “crow bar” condi-
tion for the input power rail in case the high side
10uA
DRVH
MOSFET is failed short. The crow bar operation
may trip the input supply to prevent the load from
OCP
Out
+
ILIM
OUTPUT
seeing more voltage.
P o w er Good Output
-
DRVL
The power good is an open collector output. The
PWRGD pin is pulled low at start up if any of the
two feedback voltages below 90% of its regulation
Figure 2. Block diagram of over current
protection.
level. The ramp down threshold of the signal is 80%
of the regulation target. External pull up is re-
quired for the PWRGD pin, and the pull up resistor
should be chosen such that the pin does not sink
more than 2mA when PWRGD is low.
? 2005 Semtech Corp.
9
www.semtech.com
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