参数资料
| 型号： | SC410MLTRT |
| 厂商： | Semtech |
| 文件页数： | 16/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 10MLPD |
| 标准包装： | 1 |
| 系列： | EcoSpeed® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 7.5 V |
| 输入电压： | 5.5 V ~ 24 V |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-MLPD（3x3） |
| 其它名称： | SC410MLDKR |
SC410
Applications Information (continued)
PGOOD will transition low if the V FB pin exceeds +20% of
nominal, which is also the over-voltage shutdown thresh-
old (900mV).
Output Over-Voltage Protection
OVP (Over-Voltage Protection) becomes active as soon as
the device is enabled. The threshold is set at 750mV + 20%
While the EN pin is above 0.5V, the LDO will be activated.
While the V LDO output voltage remains below 4V (80% of
the final LDO voltage), the LDO short-cicuit protection is
enabled and limits the current to about 35mA. After the
V LDO exceeds 4.0V (80% of VLDO Final), then the LDO oper-
ates in its normal regulation mode where the current is
limited to about 100mA (see Figure 8).
(900mV). When V FB exceeds the OVP threshold, the output
goes to a tri-state with both FETs disabled and the part is
latched off. There is a 5μs delay built into the OVP detector
to prevent false transitions. PGOOD is also low after an
OVP event.
Output Under-Voltage Protection
When V FB falls to 75% of its nominal voltage (falls to
562.5mV) for eight consecutive clock cycles, the switcher
V LDO Final
80% of V LDO Final
Voltage regulating with
~100mA current limit
Sort-circuit Protection @ ~35mA
is shut off and the DH and DL drives are pulled low to turn
off the MOSFETs. The controller stays off until EN is toggled
or V IN is cycled.
Over-Temperature Protection
If the temperature rises to 145°C the device will latch off.
The device can be reactivated after the temperature is
reduced below 145°C by cycling the EN pin.
V LDO UVLO, and POR
UVLO (Under-Voltage Lock-Out) circuitry inhibits switch-
ing and tri-states the power FETs until V LDO rises above
4.0V. An internal POR (Power-On Reset) occurs when V LDO
exceeds 4.0V, which resets the fault latch and soft start
counter to begin the soft start cycle. The SC410 then
begins a soft start cycle. The PWM will shut off if V LDO falls
below 3.7V.
Internal LDO Regulator
The SC410 has an internal regulator that supplies the bias
voltage for the PWM controller. This LDO can also supply
an additional external current for an external load through
the LDO pin.
When activated, the LDO checks the status of the
following signals to ensure proper operation can be
maintained.
1. EN pin
Figure 8 — LDO Start-Up
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be specified.
The maximum input voltage (V INMAX ) is the highest speci-
fied input voltage. The minimum input voltage ( V INMIN ) is
determined by the lowest input voltage after evaluating
the voltage drops due to connectors, fuses, switches, and
PCB traces.
The following parameters define the design.
? Nominal output voltage (V OUT )
? Static or DC output tolerance
? Transient response
? Maximum load current (I OUT )
The two values of load current to evaluate are continuous
load current and peak load current. Continuous load
current relates to thermal stresses which drive the selec-
tion of the inductor and input capacitors. Peak load current
determines instantaneous component stresses and filter-
ing requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
2. V LDO output voltage
3. VIN input voltage
16
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