参数资料
| 型号： | SC410MLTRT |
| 厂商： | Semtech |
| 文件页数： | 19/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 10MLPD |
| 标准包装： | 1 |
| 系列： | EcoSpeed® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 7.5 V |
| 输入电压： | 5.5 V ~ 24 V |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-MLPD（3x3） |
| 其它名称： | SC410MLDKR |
SC410
Applications Information (continued)
E SR MIN
StabilityConsiderations
Unstable operation is possible with adaptive on-time con-
trollers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
minimum off-time has expired. In extreme cases the noise
can cause three or more successive on-times. Double-
pulsing will result in higher ripple voltage at the output,
but in most applications it will not affect operation. This
form of instability can usually be avoided by providing the
FB pin with a smooth, clean ripple signal that is at least
10mVp-p, which may dictate the need to increase the ESR
of the output capacitors. It is also imperative to provide a
proper PCB layout.
An alternate method to eliminate doubling-pulsing is to
add a small (~ 10pF) capacitor across the upper feedback
resistor, as shown in Figure 9. This capacitor should be left
unpopulated unless it can be confirmed that double-
pulsing exists. Adding the C TOP capacitor will couple more
ripple into FB to help eliminate the problem. An optional
connection on the PCB should be provided for this
capacitor.
C TOP
One simple method of solving this problem is to add trace
resistance in the high current output path. A side effect of
adding trace resistance is a decrease in load regulation.
ESR Requirements
A minimum ESR is required for two reasons. The first
reason is to generate enough output ripple voltage to
provide 10mVp-p at the FB pin (after the resistor divider)
to avoid double-pulsing.
The second reason is to prevent instability due to insuffi-
cient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and dis-
charging during the switching cycle. For most applica-
tions, the total output ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching fre-
quency. The formula for minimum ESR is shown by the
following equation.
3
2 C OUT f sw
Using Ceramic Output Capacitors
When applications use ceramic output capacitors, the ESR
is normally too small to meet the previously stated ESR
V OUT
R1
R2
To FB pin
criteria. In these applications it is necessary to add a small
signal injection network as shown in Figure 10. In this
network R L and C L filter the LX switching waveform to
generate an in-phase ripple voltage comparable to the
ripple seen on higher ESR capacitors. C C is a coupling
capacitor used to AC couple the generated ripple onto the
Figure 9 — Capacitor Coupling to FB Pin
FB pin.
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking sta-
bility is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
19
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