参数资料
| 型号： | SC410MLTRT |
| 厂商： | Semtech |
| 文件页数： | 20/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 10MLPD |
| 标准包装： | 1 |
| 系列： | EcoSpeed® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 7.5 V |
| 输入电压： | 5.5 V ~ 24 V |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-MLPD（3x3） |
| 其它名称： | SC410MLDKR |
SC410
Applications Information (continued)
Output Voltage Dropout
High-
side
R L
L
C L
The output voltage adjustable range for continuous-con-
duction operation is limited by the fixed 320ns (typical)
minimum off-time. When working with low input volt-
ages, the duty-factor limit must be calculated using worst-
t ON ( MIN )
t ON ( MIN )
t OFF ( MAX )
Low-
side
C C
FB
pin
R1
R2
C OUT
case values for on and off times. The duty-factor limitation
is shown by the next equation.
DUTY
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
Figure 10 — Signal Injection Circuit
The values of R L , C L , and C C are dependent on the condi-
tions of the specific application such as V IN , V OUT , f SW and
I OUT .
Select a value for C L , like 10nF. Using C L , calculate R L as
shown in the following equation:
dropout duty-factor calculations.
System DC Accuracy — V OUT Controller
Three factors affect V OUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static condi-
tions it trips when the feedback pin is 750mV, + 1%.
R L
C L
L
DCR
The on-time pulse from the SC410 in the design example
is calculated to give a pseudo-fixed frequency of 500kHz.
Some frequency variation with line and load is expected.
Where L is the inductor value and DCR is the resistance of
the inductor.
The value for C C can be between C C_MIN and C C_MAX .
This variation changes the output ripple voltage. Because
adaptive on-time converters regulate to the valley of the
output ripple, ? of the output ripple appears as a DC regu-
lation error.
C C _ MIN
C C _ MAX
t ON
R EQ
T
R EQ
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capaci-
tor. This trace resistance should be optimized so that at
Where T = 1/f SW and R EQ is represented by the following
equation.
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capaci-
tance because the voltage excursions due to load steps
R EQ
R BOTTOM
R TOP
R BOTTOM R TOP
are reduced as seen at the load.
The use of 1% feedback resistors may result in up to an
It is beneficial to use the smallest value of C C that provides
stability and enough voltage ripple at feedback. Larger
additional 1% error. If tighter DC accuracy is required,
resistors with lower tolerances should be used.
values of C C may negatively affect the load regulation
performance.
20
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