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| 型号： | SCC68692E1N40,602 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC DUART 40DIP |
| 标准包装： | 9 |
| 特点： | 故障启动位检测 |
| 通道数： | 2，DUART |
| FIFO's： | 3 位 |
| 电源电压： | 5V |
| 带并行端口： | 是 |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-DIP |
| 包装： | 管件 |
| 其它名称： | 935027050602 SCC68692E1N40 SCC68692E1N40-ND |
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Philips Semiconductors
Product data
SCC68692
Dual asynchronous receiver/transmitter (DUART)
2004 Mar 03
24
controlled by the receiver and the transmitter at the same time is
allowed, but would usually be incompatible.
RTS can also be controlled by the commands 1000 and 1001 in the
command register. RTS is expressed at the MP0 pin which is still an
output port. Therefore, the state of MP0 should be set LOW (either
by commands of the CR register or by writing to the Set Output
Ports Register) for the receiver to generate the proper RTS signal.
The logic at the output is basically a NAND of the MP0 bit register
and the RTS signal as generated by the receiver. When the RTS
flow control is selected via the MR(7) bit the state of the MP0
register is not changed. Terminating the use of “Flow Control” (via
the MR registers) will return the MP0 pin to the control of the MP0
register.
Transmitter Disable Note
The sequence of instructions enable transmitter — load transmit
holding register — disable transmitter will result in nothing being
sent if the time between the end of loading the transmit holding
register and the disable command is less that 3/16 bit time in the
16x mode or one bit time in the 1x mode. Also, if the transmitter,
while in the enabled state and underrun condition, is immediately
disabled after a single character is loaded to the transmit holding
register, that character will not be sent.
In general, when it is desired to disable the transmitter before the
last character is sent AND the TxEMT bit is set in the status register
(TxEMT is always set if the transmitter has underrun or has just
been enabled), be sure the TxRDY bit is active immediately before
issuing the transmitter disable instruction. TxRDY sets at the end of
the “start bit” time. It is during the start bit that the data in the
transmit holding register is transferred to the transmit shift register.
Non-standard baud rates are available as shown in Table 6 below,
via the BRG Test function.
The test mode at address H‘2’ changes all transmitters and
receivers to the 1x mode and connects the output ports to some
internal nodes.
Table 6.
Baud Rate
Normal BRG
BRG Test
CSR[7:4]
ACR[7] = 0
ACR[7] = 1
ACR[7] = 0
ACR[7] = 1
0000
50
75
4,800
7,200
0001
110
880
0010
134.5
1,076
0011
200
150
19.2K
14.4K
0100
300
28.8K
0101
600
57.6K
0110
1,200
115.2K
0111
1,050
2,000
1,050
2,000
1000
2,400
57.6K
1001
4,800
1010
7,200
1,800
57.6K
14.4K
1011
9,600
1100
38.4K
19.2K
38.4K
19.2K
1101
Timer
1110
I/O2 – 16X
1111
I/O2 – 1X
NOTE:
Each read on address H‘A’ will toggle the baud rate test mode.
When in the BRG test mode, the baud rates change as shown to the
left. This change affects all receivers and transmitters on the
DUART. See
“Extended baud rates for SCN2681, SCN68681,
SCC2691, SCC2692, SCC68681 and SCC2698B” in application
notes elsewhere in this publication
Receiver Reset in the Normal Mode (Receiver Enabled)
Reset can be accomplished easily by issuing a receiver software or hardware reset followed by a receiver enable. All receiver data,
status and programming will be preserved and available before reset. The reset will NOT affect the programming.
Receiver Reset in the Wake-Up Mode (MR1[4:3] = 11)
Reset can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software or
hardware reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and
available before reset. The reset will NOT affect other programming.
The reason for this is the receiver is partially enabled when the parity bits are at ‘11’. Thus the receiver disable and reset is bypassed by
the partial enabling of the receiver.
SD00097
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