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| 型号： | SCC68692E1N40,602 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 3/28页 |
| 文件大小： | 0K |
| 描述： | IC DUART 40DIP |
| 标准包装： | 9 |
| 特点： | 故障启动位检测 |
| 通道数： | 2，DUART |
| FIFO's： | 3 位 |
| 电源电压： | 5V |
| 带并行端口： | 是 |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-DIP |
| 包装： | 管件 |
| 其它名称： | 935027050602 SCC68692E1N40 SCC68692E1N40-ND |
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Philips Semiconductors
Product data
SCC68692
Dual asynchronous receiver/transmitter (DUART)
2004 Mar 03
11
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which
identifies the corresponding data bits as data while
MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which
identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bits into the THR.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RHR FIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RHR. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
break detect operate normally whether or not the receive is enabled.
PROGRAMMING
The operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems. For example, changing the number of bits per
character while the transmitter is active may cause the transmission
of an incorrect character. In general, the contents of the MR, the
CSR, and the OPCR should only be changed while the receiver(s)
and transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1x by
RESET or by issuing a ‘reset pointer’ command via the
corresponding command register. Any read or write of the mode
register while the pointer is at MR1x, switches the pointer to MR2x.
The pointer then remains at MR2x, so that subsequent accesses are
always to MR2x unless the pointer is reset to MR1x as described
above.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions. The reserved registers
at addresses H‘02’ and H‘0A’ should never be read during normal
operation since they are reserved for internal diagnostics.
Table 1.
Register Addressing
A3
A2
A1
A0
READ (RDN = 0)
WRITE (WRN = 0)
0
Mode Register A (MR1A, MR2A)
0
1
Status Register A (SRA)
Clock Select Register A (CSRA)
0
1
0
BRG Test
Command Register A (CRA)
0
1
Rx Holding Register A (RHRA)
Tx Holding Register A (THRA)
0
1
0
Input Port Change Register (IPCR)
Aux. Control Register (ACR)
0
1
0
1
Interrupt Status Register (ISR)
Interrupt Mask Register (IMR)
0
1
0
Counter/Timer Upper Value (CTU)
C/T Upper Preset Value (CRUR)
0
1
Counter/Timer Lower Value (CTL)
C/T Lower Preset Value (CTLR)
1
0
Mode Register B (MR1B, MR2B)
1
0
1
Status Register B (SRB)
Clock Select Register B (CSRB)
1
0
1
0
1X/16X Test
Command Register B (CRB)
1
0
1
Rx Holding Register B (RHRB)
Tx Holding Register B (THRB)
1
0
Interrupt Vector Register (IVR)
1
0
1
Input Ports IP0 to IP6
Output Port Conf. Register (OPCR)
1
0
Start Counter Command
Set Output Port Bits Command
1
Stop Counter Command
Reset Output Port Bits Command
* See Table 6 for BRG Test frequencies in this data sheet, and
“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
MR1A – Channel A Mode Register 1
MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRA. After reading or writing MR1A, the pointer will point
to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send Control
This bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full.
However, OPR[0] is not reset and RTSAN will be asserted again
when an empty FIFO position is available. This feature can be used
for flow control to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input of the transmitting
device.
MR1A[6] – Channel A Receiver Interrupt Select
This bit selects either the Channel A receiver ready status (RxRDY)
or the Channel A FIFO full status (FFULL) to be used for CPU
interrupts. It also causes the selected bit to be output on OP4 if it is
programmed as an interrupt output via the OPCR.
MR1A[5] – Channel A Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block’
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
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