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参数资料
| 型号： | SCC68692E1N40,602 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 6/28页 |
| 文件大小： | 0K |
| 描述： | IC DUART 40DIP |
| 标准包装： | 9 |
| 特点： | 故障启动位检测 |
| 通道数： | 2，DUART |
| FIFO's： | 3 位 |
| 电源电压： | 5V |
| 带并行端口： | 是 |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-DIP |
| 包装： | 管件 |
| 其它名称： | 935027050602 SCC68692E1N40 SCC68692E1N40-ND |
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Philips Semiconductors
Product data
SCC68692
Dual asynchronous receiver/transmitter (DUART)
2004 Mar 03
14
Table 2.
Register Bit Formats (Continued)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DELTA
IP3
DELTA
IP2
DELTA
IP1
DELTA
IP0
IP3
IP2
IP1
IP0
IPCR
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IN PORT
CHANGE
DELTA
BREAK B
RxRDY/
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDY/
FFULLA
TxRDYA
ISR
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IN PORT
CHANGE
INT
DELTA
BREAK B
INT
RxRDY/
FFULLB
INT
TxRDYB
INT
COUNTER
READY
INT
DELTA
BREAK A
INT
RxRDY/
FFULLA
INT
TxRDYA
INT
IMR
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
C/T[15]
C/T[14]
C/T[13]
C/T[12]
C/T[11]
C/T[10]
C/T[9]
C/T[8]
CTUR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
C/T[7]
C/T[6]
C/T[5]
C/T[4]
C/T[3]
C/T[2]
C/T[1]
C/T[0]
CTLR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IVR[7]
IVR[6]
IVR[5]
IVR[4]
IVR[3]
IVR[2]
IVR[1]
IVR[0]
IVR
MR2A[3:0] – Channel A Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to
2 bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1–1/16
to 2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a ‘mark’ condition at the center
of the first stop bit position (one bit time after the last data bit, or
after the parity bit is enabled).
If an external 1X clock is used for the transmitter, MR2A[3] = 0
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
transmitted.
MR1B – Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will point
to MR2B.
The bit definitions for this register are identical to MR1A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs.
MR2B – Channel B Mode Register 2
MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
The bit definitions for mode register are identical to the bit definitions
for MR2A, except that all control actions apply to the Channel B
receiver and transmitter and the corresponding inputs and outputs.
Table 3.
Baud Rate
CSRA[7:4]
ACR[7] = 0
Baud Rate ACR[7] = 1
0000
50
75
0001
110
0010
134.5
0011
200
150
0100
300
0101
600
0110
1,200
0111
1,050
2,000
1000
2,400
1001
4,800
1010
7,200
1,800
1011
9,600
1100
38.4k
19.2k
1101
Timer
1110
IP4–16X
1111
IP4–1X
NOTE: The receiver clock is always a 16X clock except for CSRA[7:4] = 1111.
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