参数资料
型号: SDA20C440
厂商: SIEMENS A G
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PQFP80
封装: PLASTIC, MQFP-80
文件页数: 10/55页
文件大小: 990K
代理商: SDA20C440
SDA 20C440
Semiconductor Group
18
2.4
Processor Reset and Clock Circuit
Processor Reset and Initialization
A low level at pin RESET for at least 4
s resets the processor. All port lines are set to input mode.
After reset, most special function registers are set to 00H, except for:
q
Stack Pointer Register (set to 07H)
q
Oscillator Control Register (set to 01H)
(for detail see chapter ‘Memory Organization’)
Important Note: When entering reset, port lines P0.0 and P0.1 are to be held at high level (or left
open). Otherwise the processor test mode is entered.
Processor Clock Circuit
The internal processor clock is derived from an external reference, which may be a quartz/ceramic
resonator or an RC-oscillator (selected by mask option). The reference frequency is 4 MHz, the
internal operating frequency is 12 MHz. See chapter ‘AC-Characteristics’ for reference frequency
limits.
The operating frequency is generated by a PLL circuit. After reset, the PLL is disabled and the
processor runs at the external reference frequency (4 MHz). By setting the oscillator control register
(OSCON, see below), the operating frequency is set to 12 MHz. Once being activated, the PLL
cannot be switched off any more. The following sequence is to be used for initializing the clock
system after reset:
MOV OSCON,#41H
MOV OSCON,#10H
This should be done before using one of the peripheral modules (timer, LCD-unit etc.)
PLLD:
PLL disable
= 1: PLL is deactivated
= 0: PLL is activated
Note: After activating the PLL once after reset, a deactivation is not possible any more.
OSC, OSF:
Oscillator frequency select for 12-MHz system clock
(see initialization sequence)
Default after reset:
01H
MSB
SFR-Address: 9AH
LSB
OSCON: Oscillator Control Register
...
OSC
...
OSF
...
PLLD
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