![](http://datasheet.mmic.net.cn/140000/SDA20C440_datasheet_5012068/SDA20C440_25.png)
SDA 20C440
Semiconductor Group
25
Data Reception
In idle state the dataline on pin RXD is held at high level. The beginning of a data byte starts with
the first ‘1 – 0’ transition (start bit), which also synchronizes the baudrate generator. After this, eight
or nine data bits are read according to the selected mode with the clock of the baudrate generator.
In mode II the parity of the data byte is compared with the parity bit automatically. The stop bit is
always tested for the value ‘1’. If an error is detected, the appropriate error flag is set and causes an
interrupt, if enabled.
In case of no error, the received data byte is written into the register RXBUF and at the same time
the reception is signaled to the CPU using interrupt RXINT. If the data byte in the receive register
RXBUF is to be overwritten by a new data byte before the CPU has read this register, the overwrite
error flag is set and the control interrupt is activated.
Data Transmission
The transmission of a data word is started automatically by writing to the transmit register. The data
word of register TXBUF is loaded into the shift register TSREG. With the clock of the baudrate
generator the data value is shifted to pin TXD. The data word consists of an automatically generated
start bit, eight or nine data bits and one stop bit. In mode II the parity bit is computed and is
transmitted as the nineth data bit.
Transmit and Receive Register
The CPU writes the data to be sent into the transmit buffer TXBUF. It is a special function register
with write-only access. While reading from this address location, the receive register RXBUF will be
available.
Receive-Register
The SART-module writes the received data into the receive register RXBUF. It is a special-function-
register with ‘read-only’ access. While writing with this address the transmit register will be written.
MSB
SFR-Address: C3H
LSB
SABUF: Serial Port Transmit/Receive Buffer
D7
D6
D5
D4
D3
D2
D1
D0