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参数资料
| 型号： | SED122ADXA |
| 元件分类： | 显示控制器 |
| 英文描述： | 16 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC165 |
| 封装： | DIE-165 |
| 文件页数： | 27/50页 |
| 文件大小： | 398K |
| 代理商： | SED122ADXA |
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SED1220
EPSON
4–33
SED1220
*5: Character “
” display. This is applicable to the
case where no access is made from the MPU and the
built-in power circuit and oscillating circuit are in
operation.
*6: Current consumption when data is always written by
fcyc.
The current consumption in the access state is almost
proportional to the access frequency (fcyc).
When no access is made, only IDD (I) occurs.
*7:
tR (reset time) indicates the internal circuit reset
completion time from the edge of the RES signal.
Accordingly, the SED1220 usually enters the oper-
ating state after
tR.
*8: Specifies the minimum pulse width of the RES
signal. It is reset when a signal having the pulse
width greater than
tRW is entered.
*9: When operating the boosting circuit, the power
supply VSS must be used within the input voltage
range.
*10: The fOSC frequency of the oscillator circuit for
internal circuit drive may differ from the fBST boost-
ing clock on some models. The following provides
the relationship between the fOSC frequency, fBST
boosting clock, and fFR frame frequency.
fOSC = (No. of digits)
× (1/Duty) × fFR
fBST = (1/2)
× (1/No. of digits) × fOSC
*11: When performing the operations using an external
clock, not taking advantage of the built-in oscillation
circuit, input the waveforms indicated below.
Meanwhile, while using an external clock but when
clock inputs are not being made, fix it to “H”.
(Normal High)
<Incase the external clock = fosc>
Duty = (th/tosc)
× 100 = 20 ~ 30%
fosc = 1/tosc
<Incase the external clock = 4
× fosc>
Duty = (th/tosc)
× 100 = 50%
fosc = 1/tosc
Power Supply
tRES
VDD
VSS
VDD
VSS
–2.4 V
tRW
tR
RES
All signal timings are based on 20% and 80% of VSS signals.
tosc
th
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相关代理商/技术参数 |
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| SED1278 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER |
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