参数资料
型号: SED122ADXA
元件分类: 显示控制器
英文描述: 16 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC165
封装: DIE-165
文件页数: 29/50页
文件大小: 398K
代理商: SED122ADXA
SED1220
EPSON
4–35
SED1220
(2)
MPU Bus Write Timing (68 series)
Item
Signal
Symbol
Measuring
Min.
Max.
Unit
condition
Address setup time
A0, CS
tAW6
Every timing is specified
60
ns
Address hold time
tAH6
on the basis of 20% and
30
ns
CS setup time
tAC6
80% of VSS.0
ns
System cycle time
WR
tCYC6
650
ns
Enable “L” pulse width (WR)
tEWL
150
ns
Enable “H” pulse width (WR)
tEWH
450
ns
Data setup time
D0 ~ D7
tDS6
100
ns
Data hold time
tDH6
50
ns
[Ta = –30 to 85
°C, VSS = –3.6 V to –2.4 V]
Item
Signal
Symbol
Measuring
Min.
Max.
Unit
condition
Address setup time
A0, CS
tAW6
Every timing is specified
60
ns
Address hold time
tAH6
on the basis of 20% and
10
ns
CS setup time
tAC6
80% of VSS.0
ns
System cycle time
WR
tCYC6
500
ns
Enable “L” pulse width (WR)
tEWL
100
ns
Enable “H” pulse width (WR)
tEWH
350
ns
Data setup time
D0 ~ D7
tDS6
100
ns
Data hold time
tDH6
20
ns
[Ta = –30 to 85
°C, VSS = –3.3 V to –2.7 V]
*1: For the rise and fall of an input signal (tr and tf), set a value not exceeding 25ns (excluding RES input).
*2: tEWH is specified based on an overlap period of CS “L” and E “H” levels.
VSS
× 0.8 [V]
VSS
× 0.2 [V]
tr
tf
tCYC6
tAW6
tEWL
tAC6
tEWH
tAH6
tDS6
tDH6
E
CS
A0
D0 to D7
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