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| 型号： | SFCF2048H2BU2TO-I-MS-517-STD |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 25/102页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 2GB |
| 标准包装： | 1 |
| 系列： | C-440 |
| 存储容量： | 2GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1094 |
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Table 25: Ultra DMA Signal Usage in Each Interface Mode
UDMA Signal
DMARQ
DMACK
Type
Output
Input
Pin # (Non UDMA
MEM MODE)
43 (-INPACK)
44 (-REG)
PC CARD MEM
MODE UDMA
-DMARQ
-DMACK
PC CARD IO
MODE UDMA
-DMARQ
DMACK
TRUE IDE MODE
UDMA
DMARQ
-DMACK
STOP
Input
35 (-IOWR)
STOP
1
STOP
1
STOP
1
-HDMARDYI
HSTROBE(W)
-HDMARDYI
HSTROBE(W)
-HDMARDYI
HSTROBE(W)
HDMARDYI
HSTROBE(W)
Input
34 (-IORD)
1, 2
1, 3, 4
1, 2
1, 3, 4
1, 2
1, 3, 4
DSTROBEI
DSTROBEI
DSTROBEI
DDMARDY(W)
DSTROBEI
DATA
ADDRESS
CSEL
Output 42 (-WAIT)
Bidir
(D[15:0])
Input
(A[10:0])
Input
39 (-CSEL)
-DDMARDY(W)
1. 2. 4
D[15:0]
A[10:0]
-CSEL
1, 3
-DDMARDY(W)
1. 2. 4
D[15:0]
A[10:0]
-CSEL
1, 3
-DDMARDY(W)
1. 2. 4
D[15:0]
5
A[02:0]
-CSEL
1, 3
INTRQ
Output 37 (READY)
READY
-INTRQ
INTRQ
Card Select
Input
7 (-CE1)
31 (-CE2)
-CE1
-CE2
-CE1
-CE2
-CS0
-CS1
Notes:
1.
2.
The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.
The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read
command.
3. The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write
command.
4. The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.
5. Address lines 03 through 10 are not used in True IDE mode.
Several signal lines are redefined to provide different functions during an Ultra DMA burst. These lines assume
these definitions when:
1.
2.
an Ultra DMA mode is selected, and
a host issues a READ DMA, or a WRITE DMA command requiring data transfer, and
3. the device asserts (-)DMARQ, and
4. the host asserts – DMACK.
These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of – DMACK by
the host at the termination of an Ultra DMA burst.
With the Ultra DMA protocol, the STROBE signal that latches data from D[15:0] is generated by the same agent
(either host or device) that drives the data onto the bus. Ownership of D[15:0] and this data strobe signal are
given either to the device during an Ultra DMA data-in burst or to the host for an Ultra DMA data-out burst.
During an Ultra DMA burst a sender shall always drive data onto the bus, and, after a sufficient time to allow for
propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data.
Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency
as the data.
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is
capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host
to select the Ultra DMA mode at which the system operates. The Ultra DMA mode selected by a host shall be less
than or equal to the fastest mode of which the device is capable. Only one Ultra DMA mode shall be selected at
any given time. All timing requirements for a selected Ultra DMA mode shall be satisfied. Devices supporting any
Ultra DMA mode shall also support all slower Ultra DMA modes.
An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software reset
sequence or the sequence caused by receipt of a DEVICE RESET command if a SET FEATURES disable reverting to
defaults command has been issued. The device may revert to a Multiword DMA mode if a SET FEATURES enable
reverting to default has been issued. An Ultra DMA capable device shall clear any previously selected Ultra DMA
mode and revert to the default non-Ultra DMA modes after executing a power-on or hardware reset.
Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the
host sends its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two
values do not match, the device reports an error in the error register. If an error occurs during one or more Ultra
DMA bursts for any one command, the device shall report the first error that occurred. If the device detects that a
CRC error has occurred before data transfer for the command is complete, the device may complete the transfer
and report the error or abort the command and report the error.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 25 of 102
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