- 您现在的位置：买卖IC网 > PDF目录21886 > SFCF2048H2BU2TO-I-MS-517-STD (Swissbit NA Inc)FLASH SLC UDMA/MDMA/PIO 2GB PDF资料下载
参数资料
| 型号： | SFCF2048H2BU2TO-I-MS-517-STD |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 41/102页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 2GB |
| 标准包装： | 1 |
| 系列： | C-440 |
| 存储容量： | 2GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1094 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页当前第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页
6. The device shall then compare the CRC data from the host with the calculated value in its own CRC
calculation function. If the two values do not match, the device shall save the error and report it at the
end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error
shall not clear an error saved from a previous Ultra DMA burst in the same command. If a miscompare
error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the
device shall report the first error that occurred.
7.
For READ DMA, WRITE DMA, READ DMA QUEUED, or WRITE DMA QUEUED commands:
When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error
register) to one. ICRC is defined as the “Interface CRC Error” bit. The host shall respond to this error by re-
issuing the command.
8. For a REQUEST SENSE packet command (see SPC T10/955D for definition of the REQUEST SENSE command):
When a CRC error is detected during transmission of sense data the device shall complete the command
and set CHK to one. The device shall report a Sense key of 0Bh (ABORTED COMMAND). The device shall
preserve the original sense data that was being returned when the CRC error occurred. The device shall
not report any additional sense data specific to the CRC error. The host device driver may retry the REQUEST
SENSE command or may consider this an unrecoverable error and retry the command that caused the
Check Condition.
9. For any packet command except a REQUEST SENSE command: If a CRC error is detected, the device shall
complete the command with CHK set to one. The device shall report a Sense key of 04h (HARDWARE
ERROR). The sense data supplied via a subsequent REQUEST SENSE command shall report an ASC/ASCQ value
of 08h/03h (LOGICAL UNIT COMMUNICATION CRC ERROR). Host drivers should retry the command that resulted
in a HARDWARE ERROR.
NOTE – If excessive CRC errors are encountered while operating in Ultra mode 2 or 1, the host should select
a slower Ultra mode. Caution: CRC errors are detected and reported only while operating in an Ultra
mode.
10. A host may send extra data words on the last Ultra DMA burst of a data out command. If a device
determines that all data has been transferred for a command, the device shall terminate the burst. A
device may have already received more data words than were required for the command. These extra
words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst,
the extra words shall be discarded by the device.
11. 11. The CRC generator polynomial is: G(X) = X16 + X12 + X5 + 1. Table 30 describes the equations for 16-bit
parallel generation of the resulting polynomial (based on a word boundary).
NOTE – Since no bit clock is available, the recommended approach for calculating CRC is to use a word
clock derived from the bus strobe. The combinational logic is then equivalent to shifting sixteen bits
serially through the generator polynomial where D0 is shifted in first and D15 is shifted in last.
Table 30: Equations for parallel generation of an Ultra DMA CRC
CRCIN0 = f16
CRCIN1 = f15
CRCIN2 = f14
CRCIN3 = f13
CRCIN4 = f12
CRCIN5 = f11 XOR f16
CRCIN6 = f10 XOR f15
CRCIN7 = f9 XOR f14
f1 = D0 XOR CRCOUT15
f2 = D1 XOR CRCOUT14
f3 = D2 XOR CRCOUT13
f4 = D3 XOR CRCOUT12
f5 = D4 XOR CRCOUT11 XOR f1
f6 = D5 XOR CRCOUT10 XOR f2
f7 = D6 XOR CRCOUT9 XOR f3
f8 = D7 XOR CRCOUT8 XOR f4
Notes:
CRCIN8 = f8 XOR f13
CRCIN9 = f7 XOR f12
CRCIN10 = f6 XOR f11
CRCIN11 = f5 XOR f10
CRCIN12 = f4 XOR f9 XOR f16
CRCIN13 = f3 XOR f8 XOR f15
CRCIN14 = f2 XOR f7 XOR f14
CRCIN15 = f1 XOR f6 XOR f13
f9 = D8 XOR CRCOUT7 XOR f5
f10 = D9 XOR CRCOUT6 XOR f6
f11 = D10 XOR CRCOUT5 XOR f7
f12 = D11 XOR CRCOUT4 XOR f1 XOR f8
f13 = D12 XOR CRCOUT3 XOR f2 XOR f9
f14 = D13 XOR CRCOUT2 XOR f3 XOR f10
f15 = D14 XOR CRCOUT1 XOR f4 XOR f11
f16 = D15 XOR CRCOUT0 XOR f5 XOR f12
1.
2.
3.
4.
f=feedback
D[15:0] = Data to or from the bus
CRCOUT = 16-bit edge triggered result (current CRC)
CRCOUT[15:0] are sent on matching order bits of D[15:0]
An example of a CRC generator implementation is provided below in Figure 20: Ultra DMA Parallel CRC Generator
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 41 of 102
相关PDF资料 |
PDF描述 |
|---|---|
| MLEAWT-A1-0000-0004E5 | LED XLAMP NEUTRAL WHIT 4000K SMD |
| TSL13T | IC SENSOR LIGHT-VOLT 4-SMD |
| TSL12S-LF | IC SENSOR LIGHT-VOLT SIDELOOKER |
| TSL14S-LF | IC SENSOR LIGHT-VOLT SIDELOOKER |
| MLEAWT-A1-0000-0004A2 | LED XLAMP ML-E WHITE SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SFCF2048H2BU2TO-I-MS-527-STD | 制造商:SWISSBIT NA INC 功能描述:FLASH |
| SFCF2048H4BK1SA-C-QT-553-SMA | 制造商:SWISSBIT NA INC 功能描述:FLASH |
| SFCF2048H4BK1SA-I-QT-553-SMA | 功能描述:FLASH SLC UDMA/MDMA/PIO 2G RoHS:是 类别:存储卡，模块 >> 存储器，PC 卡 系列:C-300 标准包装:30 系列:- 存储容量:8GB 存储器类型:存储卡 - Extreme III SD? |
| SFCF2048H4BK2SA-C-DS-553-SMA | 制造商:SWISSBIT NA INC 功能描述:FLASH SLC UDMA/MDMA/PIO 2G |
| SFCF2048H4BK2SA-I-DS-553-SMA | 功能描述:FLASH SLC UDMA/MDMA/PIO 2G RoHS:是 类别:存储卡，模块 >> 存储器，PC 卡 系列:C-300 标准包装:30 系列:- 存储容量:8GB 存储器类型:存储卡 - Extreme III SD? |
发布紧急采购，3分钟左右您将得到回复。